PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 42

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

IPAC-X
PSB/PSF 21150
Description of Functional Blocks
All eight interrupt bits in the ISTA register point at interrupt sources in the D-channel
HDLC Controller (ICD), B-channel HDLC controllers (ICA, ICB), Monitor- (MOS) and C/
I- (CIC) handler, the transceiver (TRAN), the synchronous transfer (ST) and the auxiliary
interrupts (AUXI).
All these interrupt sources are described in the corresponding chapters. After the device
has requested an interrupt activating the interrupt pin (INT), the host must read first the
device interrupt status register (ISTA) in the associated interrupt service routine. The
interrupt pin of the device remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the interrupt pin is still
active when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
into the MASK register)
H
and write back the old mask to the MASK register.
Data Sheet
42
2003-01-30