PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 129

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 72
The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the
IOM-2 interface (see
generated by software (µP access to the C/I channel) or by the IPAC-X itself
(transmission of an HDLC frame in the D-channel). A software access request to the bus
is effected by setting the BAC bit (CIX0 register) to ’1’.
In the case of an access request, the IPAC-X checks the Bus Accessed-bit BAC (bit 5 of
last octet of CH2 on DU, see
a logical ’1’. If the bus is free, the IPAC-X transmits its individual TIC bus address TAD
programmed in the CIX0 register (CIX0.TBA2-0). The IPAC-X sends its TIC bus address
TAD and compares it bit by bit with the value on DU. If a sent bit set to ’1’ is read back
as ’0’ because of the access of another D-channel source with a lower TAD, the IPAC-
X withdraws immediately from the TIC bus, i.e. the remaining TAD bits are not
transmitted. The TIC bus is occupied by the device which sends its address error-free.
If more than one device attempt to seize the bus simultaneously, the one with the lowest
address values wins. This one will set BAC=0 on TIC bus and starts D-channel
transmission in the same frame.
Data Sheet
IPAC-X
D-channel
control
ICC (7)
ICC (2)
ICC (1)
.
.
.
Applications of TIC Bus in IOM-2 Bus Configuration
Figure
TIC-Bus
on IOM-2
transceiver
Figure
73). An access request to the TIC bus may either be
S-
73) for the status "bus free“, which is indicated by
129
S-Interface
Description of Functional Blocks
NT
21150_09
PSB/PSF 21150
U-Interface
2003-01-30
IPAC-X