PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet
PSB21150HV14XP
Specifications of PSB21150HV14XP
Related parts for PSB21150HV14XP
PSB21150HV14XP Summary of contents
Page 1
...
Page 2
ABM , ACE , AOP , ARCOFI ® ® FALC , GEMINAX , IDEC ® ® MUSAC , MuSLIC , OCTAT ® ® SCOUT , SICAT , SICOFI ® ® 10BaseV , 10BaseVX 10BaseS™, EasyPort™, VDSLite™ are ...
Page 3
Data Sheet Revision History: Previous Version: Page Subjects (major changes since last revision) Chapter 1 Comparison IPAC/IPAC-X Chapter S- Transceiver Synchronization New 3.3.7.2 Chapter Test Functions extended 3.3.11 Chapter CDA Handler Description extended 3.7.1.1 Chapter TIC Bus Access Control: Note ...
Page 4
Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Table of Contents 3.5.2.2 States (LT- ...
Page 6
Table of Contents 3.9.3.2 Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ...
Page 7
Table of Contents 4.2.14 TR_MODE - Transceiver Mode Register 197 4.3 Auxiliary Interface Registers . . . . ...
Page 8
Table of Contents 4.6.2 MASKB - Mask Register B-Channels . . . . . . . . . . . . . . . . . . . . . . . . . 227 4.6.3 STARB - Status Register ...
Page 9
List of Figures Figure 1 Logic Symbol of the IPAC ...
Page 10
List of Figures Figure 39 Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure ...
Page 11
List of Figures Figure 76 Data Flow for Collision Resolution Procedure in Intelligent 136 Figure 77 Deactivation of the IOM-2 Interface . . . . . . . . . . . . . ...
Page 12
List of Tables Table 1 Comparison of the IPAC-X with the Previous Version IPAC Table 2 IPAC-X Pin Definitions and Functions . . . . . . . . . . . ...
Page 13
Overview The ISDN PC Adapter Circuit Extended IPAC-X integrates all necessary functions for a host based ISDN access solution on a single chip based on the IPAC PSB 2115, and provides enhanced features and functionality. It includes ...
Page 14
Table 1 Comparison of the IPAC-X with the Previous Version IPAC: Operating modes Supply voltage Technology Package Transceiver Transformer ratio for the transmitter receiver Test Functions Microcontroller Interface Crystal Buffered 7.68 MHz output Controller data access to IOM-2 timeslots Data ...
Page 15
Monitor channel programming C/I channels Layer 1 state machine Layer 1 state machine in software Support of IDSL (144kBit/s) Provided D-channel HDLC support D-channel FIFO size B-channel HDLC support B-channel FIFO size Reset Sources Interrupt Output Signals Data Sheet IPAC-X ...
Page 16
Auxiliary Interface PCM Interface Functions FBOUT, INT0/1 Reset Signals Pin SCLK Timeslots of arbitrary lenght not available Data Sheet IPAC-X PSB 21150 Provided Not Provided Provided RES input signal RSTO output signal 1.536 MHz 16 IPAC-X PSB/PSF 21150 Overview ...
Page 17
IPAC-X ISDN PC Adapter Circuit V 1.4 1.1 Features • Single chip host based ISDN solution • Based on IPAC PSB 2115, integrating ISAC-S and HSCX-TE functionality • 8-bit parallel microcontroller interface, Motorola and Siemens/Intel bus type multiplexed or non-multiplexed, ...
Page 18
Adaptively switched receive thresholds • Auxiliary Interface with general purpose I/O pins and LED drivers • Two programmable timers • Watchdog timer • Test loops • Sophisticated power management for restricted power mode • Power supply 3.3 V • ...
Page 19
Logic Symbol The logic symbol gives an overview of the IPAC-X functions. It must be noted that not all functions are available simultaneously, but depend on the selected mode. Pins which are marked with a “ * “ are ...
Page 20
Typical Applications The IPAC-X can be used in a variety of applications like • ISDN PC adapter card for S interface • ISDN PC adapter card for interface • ISDN voice/data terminal • ISDN stand-alone terminal ...
Page 21
An ISDN adapter card which supports both U and S interface may be realized using the IPAC-X together with the PSB 21911 IEC-Q TE. The S interface may be configured for TE or LT-S mode supporting intelligent NT applications. S ...
Page 22
The figure below shows a voice data terminal developed card where the IPAC- X provides its functionality as data controller and S interface within a two chip solution. During ISDN calls the PSB 2163 ARCOFI-SP provides speakerphone ...
Page 23
The IPAC-X can be integrated in a microcontroller based stand-alone terminal that is connected to the communications interface of a PC. The SICOFI2-TE PSB 2132 enables connection of analog terminals (e.g. telephone or fax) to the dual channel POTS interface. ...
Page 24
Pin Configuration BCL / SCLK DU DD FSC DCL VSS VSS VDD MODE0 MODE1 / EAW ACL AUX7 AUX6 AUX5 AUX4 AUX3 Figure 6 Pin Configuration of the IPAC-X Data Sheet P-MQFP-64-1 P-TQFP-64 ...
Page 25
Table 2 IPAC-X Pin Definitions and Functions Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD) Host Interface ...
Page 26
Table 2 IPAC-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD) 15 AD6 I/O SDR I 16 AD7 I/O SDX R/W I ...
Page 27
Table 2 IPAC-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD) 41 ALE INT OD (O) 5 RES I 38 AMODE I IOM-2 Interface 52 FSC ...
Page 28
Table 2 IPAC-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD) 49 BCL/ O SCLK 51 DD I/O (OD I/O (OD) 29 SDS1 O 28 SDS2 O Auxiliary Interface ...
Page 29
Table 2 IPAC-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD) 63 AUX4 I/O (OD) 62 AUX5 I/O (OD) 61 AUX6 I/O (OD) Data Sheet Function • Auxiliary Port 4 (input/output) ...
Page 30
Table 2 IPAC-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD) 60 AUX7 I/O (OD) Miscellaneous 43 SX1 O 44 SX2 O 47 SR1 I 48 SR2 I 35 XTAL1 I ...
Page 31
Table 2 IPAC-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD) 58 MODE1 I EAW I 59 ACL O 27 C768 O 6 RSTO n.c. ...
Page 32
Table 2 IPAC-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) MQFP-64 Output (O) TQFP-64 Open Drain (OD 17, 34, – SS 37, 54 – SSA Data Sheet Function Digital ground (0 V) ...
Page 33
Description of Functional Blocks 3.1 General Functions and Device Architecture Figure 7 shows the architecture of the IPAC-X containing the following functions: • S/T-interface transceiver • Serial or parallel microcontroller interface • Two B-channel HDLC-controller with 128 byte FlFOs ...
Page 34
Microcontroller Interfaces The IPAC-X supports a serial or a parallel microcontroller interface. For applications where no controller is connected to the IPAC-X microcontroller interface programming is done via the IOM-2 MONITOR channel from a master device. In such applications ...
Page 35
Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the ...
Page 36
Programming Sequences The basic structure of a read/write access to the IPAC-X registers via the serial control interface is shown in Figure write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 9 Serial Control Interface Timing ...
Page 37
Header 40 : Non-interleaved A-D-A-D Sequences H The non-interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one ...
Page 38
Header 41 : Non-interleaved A-D-D-D Sequence H This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of ...
Page 39
Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows easy and fast microcontroller access. The parallel interface of the IPAC-X provides three types buses which are selected via pin ALE. The ...
Page 40
Indirect Address Mode MODE2:AMOD=1 Address Figure 10 Direct/Indirect Register Address Mode Data Sheet Description of Functional Blocks Direct Address Mode MODE2:AMOD=0 Data Address AD0-7 A0-7 8Fh 8Eh Address DATA 01h ADDRESS 00h 40 IPAC-X PSB/PSF 21150 Data ...
Page 41
Interrupt Structure Special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. Since only one interrupt request pin ...
Page 42
All eight interrupt bits in the ISTA register point at interrupt sources in the D-channel HDLC Controller (ICD), B-channel HDLC controllers (ICA, ICB), Monitor- (MOS) and C/ I- (CIC) handler, the transceiver (TRAN), the synchronous transfer (ST) and the auxiliary ...
Page 43
Reset Generation Figure 12 shows the organization of the reset generation of the device. . 125µs £ t £ 250µs C/I Code Change (Exchange Awake) 125µs £ t £ 250µs EAW (Subscriber Awake) 125µs £ t £ 250µs Watchdog ...
Page 44
Table 6 Reset Source Selection RSS2 RSS1 Bit 1 Bit • C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates an external reset pulse of 125 ...
Page 45
BCL clock cycles. The address range of the registers which will be reset at each SRES bit is listed in 3.2.5 Timer Modes The IPAC-X provides two timers which can be used ...
Page 46
Timer 1 The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is generated continuously if CNT single ...
Page 47
Activation Indication via Pin ACL The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as ...
Page 48
S/T-Interface The layer-1 functions for the S/T interface of the IPAC-X are: – Line transceiver functions for the S/T interface according to the electrical specifications of ITU-T I.430; – Conversion of the frame structure between IOM-2 and S/T interface; ...
Page 49
IPAC IPAC-X TR LT-T 1) The maximum line attenuation tolerated by the IPAC kHz. TR IPAC-X TE1 £ £ .... IPAC-X TE1 Figure 18 Wiring Configurations in User ...
Page 50
S/T-Interface Coding Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. Line Coding The following figure illustrates the line ...
Page 51
Figure 20 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – ...
Page 52
S/T-Interface Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer 1 capacity in the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel). The Q bits are defined to be the bits in ...
Page 53
TE Mode After multi-frame synchronization has been established, the Q data will be inserted at the upstream (TE ® NT) F bit position in each 5th S/T frame (see A When synchronization is not achieved or lost, each received F ...
Page 54
Multiframe Synchronization (M-Bit) The IPAC-X offers the capability to control the start of the multiframe from external signals, so applications which require synchronization between different S-interfaces are possible. Such an application is the connection of DECT base stations to ...
Page 55
Sample Time FSC DCL FSC detected XTAL SX1 / SX2 MBIT Counter reset The sample time of the MBIT input is related to the rising edge of FSC at the beginning frame -- min ...
Page 56
(NT -> TE FSC DD ( MBIT (o) Figure 24 Frame Relationship LT-T Mode (M-Bit output) Data Sheet ...
Page 57
Data Transfer and Delay between IOM-2 and S/T TE Mode In the state F7 (Activated the internal layer-1 state machine is disabled and XINF of register TR_CMD is programmed to ’011’ the B1, B2, D and E ...
Page 58
-> -> FSC Mapping of B-Channel Timeslots Mapping of a 4-bit group of D-bits on S and IOM depends ...
Page 59
-> -> FSC Figure 27 Data Delay Between IOM-2 and S/T Interface With 8 IOM Channels (LT-S/NT mode only) E ...
Page 60
Transmitter Characteristics The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source ( mA). The equivalent circuit of the transmitter is shown in max The ...
Page 61
Receiver Characteristics The receiver consists of a differential input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. A simplified equivalent circuit of the receiver is shown in ...
Page 62
S/T Interface Circuitry For both the receive and transmit direction a 1:1 transformer is used to connect the IPAC-X transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found in the chapter on electrical characteristics. The ...
Page 63
Protection Circuit for Transmitter SX1 SX2 Figure 32 External Circuitry for Transmitter Figure 32 illustrates the secondary protection circuit recommended for the transmitter. The external resistors (5 ... are required in order to adjust the output voltage ...
Page 64
Note capacitors are optional for noise reduction Figure 33 External Circuitry for Symmetrical Receivers Between each receive line and the transformer resistor is used. This value is split into two resistors: one ...
Page 65
S-Transceiver Synchronization Synchronization problems can occur on a S-Bus that is not terminated properly. Therefore recommended to change the resistor values in the receive path. The sum of both resistors is increased from (1.8 ...
Page 66
An activation initiated from the exchange side will have the consequence that a clock signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set to ’1’ the microcontroller has to take care of an interrupt caused ...
Page 67
The transmit data of the transmitter is looped back internally to the receiver. The data of the IOM-2 input B- and D-channels are looped back to the output B- and D- channels. The S/T interface level detector is ...
Page 68
The continuous pulses are of alternating polarity. 48 pulses are transmitted in each frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding C/I command is SCP (Send Continuous Pulses). 3.4 Clock Generation Figure 37 ...
Page 69
Data Sheet Description of Functional Blocks 69 IPAC-X PSB/PSF 21150 2003-01-30 ...
Page 70
Note: The IOM-2 interface is adaptive. This means in LT-S/NT and LT-T mode other frequencies for BCL and DCL are possible in the range of 512-4096 kHz (DCL) and 256-2048 kHz (BCL). For details please refer to the application note ...
Page 71
Description of the Receive PLL (DPLL) The receive PLL performs phase tracking between the F/L transition of the receive signal and the recovered clock. Phase adjustment is done by adding or subtracting 0 XTAL period to or ...
Page 72
Oscillator Clock Output C768 The IPAC-X derives its system clocks from an external clock connected to XTAL1 (while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and XTAL2. At pin C768 a buffered 7.68 ...
Page 73
Control of Layer-1 The layer-1 activation/ deactivation can be controlled by an internal state machine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of the ...
Page 74
State machines are the key to understanding the transceiver part of the IPAC-X. They include all information relevant to the user and enable him to understand and predict the behaviour of the IPAC-X. The state diagram notation is given in ...
Page 75
Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/T- interface. – Leave for the state “F7 activated” after INFO 4 has been recognized on the S/T- interface. – Leave for any unconditional state ...
Page 76
Pending Act. TIM RSY TIM i4 F5 Unsynchronized i0*TO1 Synchronized Lost Framing ...
Page 77
SSP SCP SSP TMA SCP TIM DI Test Mode Figure 43 State Transition Diagram of Unconditional Transitions (TE, LT-T) 3.5.1.2 States (TE, LT-T) F3 Pending Deactivation State after deactivation from the S/T interface by info 0. ...
Page 78
Any signal except info detected on the S/T interface. F6 Synchronized The receiver has synchronized and detects info 2. Info 3 is transmitted to synchronize the NT. F7 Activated The receiver has synchronized and detects info 4. ...
Page 79
C/I Codes (TE, LT-T) Command Activation Request with priority class 8 Activation Request with priority class 10 Activation Request Loop ARL Deactivation Indication Reset Timing Test mode SSP Test mode SCP Note: In the activated states (AI8, AI10 or ...
Page 80
Indication Deactivation Request Reset Test Mode Acknowledge Slip Detected Resynchronization during level detect Deactivation Request from F6 Power up Activation request Activation request loop ARL Illegal Code Violation Activation indication loop Activation indication with priority class 8 Activation indication with ...
Page 81
Infos on S/T (TE, LT-T) Receive Infos on S/T (Downstream) Name info 0 info 2 info 4 info X Transmit Infos on S/T (Upstream) Name info 0 info 1 info 3 Test info 1 Test info 2 Data Sheet ...
Page 82
State Machine LT-S Mode 3.5.2.1 State Transition Diagram (LT-S) RST TIM RES Reset i0 * RES DC Any State DC RSY ARD G2 Lost Framing S ARD = AR or ARL ...
Page 83
States (LT-S) G1 Deactivated The transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. The clocks are deactivated if MODE1-CFS is set to 1. Activation is ...
Page 84
Test Mode - SCP Continuous alternating pulses are sent on the S/T-interface. 3.5.2.3 C/I Codes (LT-S) Command Abbr. Deactivation DR Request Reset RES Send Single Pulses SSP Send Continuous SCP Pulses Activation Request AR Activation Request ARL Loop Activation Indication ...
Page 85
Indication Abbr. Activation Indication AI Deactivation DI Indication 3.5.2.4 Infos on S/T (LT-S) Receive Infos on S/T (Downstream) I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 ...
Page 86
State Machine NT Mode 3.5.3.1 State Transition Diagram (NT) RST TIM RES Reset i0 * RES DC Any State AID RSY ARD G2 Lost Framing S RSY DR RSY RSY G3 Lost Framing Figure ...
Page 87
States (NT) G1 Deactivated The transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. The clocks are deactivated if the bit MODE1.CFS to 1. Activation is ...
Page 88
G4 Wait for DR Final state after a deactivation request. The transceiver remains in this state until DC is issued. Unconditional States Test Mode SSP Send Single Pulses Test Mode SCP Send Continuous Pulses 3.5.3.3 C/I Codes (NT) Command Abbr. ...
Page 89
Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code CVR Ciolation Activation Indication AI Deactivation DI Indication Data Sheet Description of Functional Blocks Code Remark 1110 Activation ...
Page 90
Command/Indicate Channel Codes (C/I0) - Overview The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams in ...
Page 91
Control Procedures 3.6.1 Example of Activation/Deactivation An example of an activation/deactivation of the S/T interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in figure 46 RSY ...
Page 92
Activation Initiated by the Terminal INFO 1 has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is received. After ...
Page 93
Activation initiated by the Network Termination NT INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 3 has ...
Page 94
IOM-2 Interface The IPAC-X supports the IOM-2 interface in linecard mode and in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates ...
Page 95
IOM-2 Frame Structure (TE Mode) The frame structure on the IOM-2 data ports (DU,DD master device in IOM-2 terminal mode is shown in Figure 49 IOM Ò -2 Frame Structure in Terminal Mode The frame is composed of ...
Page 96
IOM-2 Frame Structure (LT-S, LT-T Modes) This mode is used in LT-S and LT-T applications. The frame is a multiplex eight IOM-2 channels (DCL = 4096 kHz, described above. The reset value for assignment to one of ...
Page 97
IOM-2 Handler The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the IPAC-X and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all timeslots ...
Page 98
SDS2 SDS1 BCL/SCLK DCL FSC DD DU Figure 51 Architecture of the IOM Handler (Example Configuration) Data Sheet Description of Functional Blocks Data C/I0 B2, B1, D, Data B2 Data B1 Data D Data C/I1 Data C/I0 Data Bus ...
Page 99
Controller Data Access (CDA) With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the IPAC-X IOM-2 handler provides a very flexible solution for the host access IOM-2 time slots. The functional unit CDA ...
Page 100
TSa 1 0 Enable output input * (EN_O0) (EN_I0) CDAx0 1 0 TSa a,b = 0... the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and EN_I1, ...
Page 101
Looping Data TSa CDA10 TSa .TSS: .DPS ’0’ .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP c) Switching Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP Figure 53 Examples for Data Access via CDAxy Registers a) ...
Page 102
Figure 54 shows the timing of looping TSa from 0...11) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD 0...11 FSC ...
Page 103
Shifting TSa ® TSb within one frame (a,b: 0...11 and b ³ a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa ® TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa ...
Page 104
Monitoring Data Figure 56 gives an example for monitoring of two IOM-2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with ...
Page 105
Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). The microcontroller access to the CDAxy registers can be synchronized by means of ...
Page 106
Table 10 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
Page 107
Figure 58 shows some examples based on the timeslot structure. Figure a) shows at which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure b) is identical to example 3 above, figure c) corresponds ...
Page 108
Restrictions Concerning Monitoring and Shifting Data Due to the hardware design, there are some restrictions for the CDA shifting data function and for the CDA monitoring data function. The selection of the CDA registers is restricted if other functional blocks ...
Page 109
Example: w CDA1_CR = 00 (inputs and outputs are disabled CDA10 = 5A (example CDA10 = FF (old value of previous programming CDA1_CR = 02 (output of CDA10 is enabled CDA10 = ...
Page 110
FSC frame the HDLC/FIFO will access 2 bit, 8 bit, 10 bit, 16 bit or 18 bit. Some examples for access to IOM timeslots are given in • Example 1 shows 18-bit access ...
Page 111
S Interface Data which is read from and written to the IOM-2 interface by the B-channel controller as described in the previous chapter is received from and transmitted to the S interface (Figure 61). . Host B-channel B-channel HDLC 1 ...
Page 112
Serial Data Strobe Signal and Strobed Data Clock For timeslot oriented standard devices connected to the IOM-2 interface the IPAC-X provides two independent data strobe signals SDS1 and SDS2. Instead of a data strobe signal a strobed IOM-2 bit ...
Page 113
FSC DD, TS0 TS1 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 3: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 For all examples SDS_CONF.SDS1/2_BCL must be set to “0”. Figure ...
Page 114
Strobed IOM-2 Bit Clock The strobed IOM-2 bit clock is active during the programmed window. Outside the programmed window a ’0’ is driven. Two examples are shown in FSC DD, TS0 TS1 SDS1 (Example1) SDS1 (Example2) Setting ...
Page 115
IOM-2 Monitor Channel The IOM-2 MONITOR channel (see MONITOR channel between a master mode device and a slave mode device. The MONTIOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the transmission ...
Page 116
The MONITOR channel of the IPAC-X can be used in following applications which are illustrated in Figure 65: • master device the IPAC-X can program and control other devices attached to the IOM-2 which do not need a ...
Page 117
Handshake Procedure The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive (MR) and ...
Page 118
P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 66 MONITOR Channel Protocol (IOM-2) Data Sheet ...
Page 119
Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a ’0’ in the MONITOR Channel Active MAC status bit. After having written the ...
Page 120
A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. • A start of a transmission is initiated by the transmitter by setting the ...
Page 121
MX/MR Treatment in Error Case In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt, respectively. In the slave mode the ...
Page 122
IOM -2 Frame No (DU (DD) 0 Figure 69 Monitor Channel, Normal End of Transmission 3.7.3.3 MONITOR Channel Programming as a Master Device As a master device the IPAC-X can program and control other devices ...
Page 123
MONITOR Channel Programming as a Slave Device In applications without direct host controller connection the IPAC-X must operate in the MONITOR slave mode which can be selected by pinstrapping the microcontroller interface pins according transceiver part of the IPAC-X ...
Page 124
Programming Sequence The programming sequence is characterized by a ’1’ being sent in the lower nibble of the received address code. The data structure after this first byte and the principle of a read/ write access to a register is ...
Page 125
MONITOR Interrupt Logic Figure 70 shows the MONITOR interrupt structure of the IPAC-X. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of ...
Page 126
C/I Channel Handling The Command/Indication channel carries real-time status information between the IPAC-X and another device connected to the IOM-2 interface. 1. One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts ...
Page 127
C/I channel 0 before the first one has been read, immediately after reading of CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several consecutive codes are detected, only the first ...
Page 128
D-Channel Access Control D-channel access control is defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Collisions are possible: • on the IOM-2 interface if there is more than one ...
Page 129
ICC (7) . TIC-Bus . on IOM-2 . ICC (2) ICC (1) IPAC-X D-channel control Figure 72 Applications of TIC Bus in IOM-2 Bus Configuration The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the ...
Page 130
DU Figure 73 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the IPAC-X, the bus is identified to other devices as occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access ...
Page 131
MON0 Figure 74 Structure of Last Octet of Ch2 on DD The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface to determine if they can access the S/T bus D channel. The ...
Page 132
IPAC-X D-channel control TE 1 D-channel control D-channel control TE 8 Figure 75 D-Channel Access Control on the S-Interface S-Bus D-channel Access Control in the IPAC-X The above described priority mechanism is fully implemented in ...
Page 133
S-Bus D-Channel Control in LT-T If the TE frame structure on the IOM-2 interface is selected, the same D-channel access procedures as described in For other frame structures used in LT-T mode, D-channel access handled similarly, ...
Page 134
Table 14 IPAC-X Configuration Settings in Intelligent NT Applications Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit evaluation Note: For mode selection in the TR_MODE register the MODE1/2 bits are used to select ...
Page 135
NT D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The IPAC-X S-transceiver thus receives BAC = “1” (IOM-2 DU ...
Page 136
Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: • ...
Page 137
Activation/Deactivation of IOM-2 Interface The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and the data lines are ...
Page 138
DCL is activated such that its first rising edge occurs with the beginning of the bit following the C/I (C/I0) channel. After the clocks have been enabled this is indicated by the PU code in the C/I channel and, consequently, ...
Page 139
Asynchronous Awake (LT-S, NT, Int. NT mode) The transceiver is in power down mode (deactivated state) and MODE1.CFS=1 (TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect circuit will asynchronously pull the ...
Page 140
Auxiliary Interface 3.8.1 Mode Dependent Functions The AUX interface provides various functions, which depend on the operation mode (TE, LT-T, LT- Intelligent NT mode) selected by pins MODE0 and MODE1/EAW (see Table 15). After reset the pins ...
Page 141
INT0, INT1 In all modes two pins can be used as programmable I/O with optional interrupt input capability (default after reset, i.e. both interrupts masked). The INT0/1 pins are general input or output pins like AUX0-5 (see description above). In ...
Page 142
For DCL = 1.536 MHz one of the IOM-2 channels can be selected, for DCL = 4.096 MHz any of the eight IOM-2 channels can be selected. The channel select pins have direct effect on the timeslot ...
Page 143
HDLC Controllers The IPAC-X contains three HDLC controllers which can arbitrarily be used for the layer-2 functions of the D- channel protocol (LAPD) and B-channel protocols. By setting the Enable HDLC channel bits (EN_D, EN_B1H, EN_B2H) in the DCI_CR/BCH_CR ...
Page 144
Message Transfer Modes The HDLC controllers can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus the receive data flow and the address recognition features can be ...
Page 145
Transparent Mode 0 (MDS2-0 = ’110’). Characteristics: No address recognition Every received frame is stored in RFIFOx (first byte after opening flag to CRC field). Additional information can be read from RSTAx. Transparent Mode 1 (MDS2-0 = ’111’). Characteristics: SAPI ...
Page 146
There are three different interrupt indications in the ISTAx registers concerned with the reception of data: – RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length (EXMx.RFBS) can be read from RFIFOx. The message which ...
Page 147
If a frame is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least significant bits of RBCLx contain the number of valid bytes in the last data block indicated by RMEx (length of last data block ...
Page 148
RAM EXMx.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt ISTAx.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further data ...
Page 149
Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTAx byte will be set complete frame is lost, i.e. ...
Page 150
N In case of RME the last byte in RFIFO contains 1) * the receive status information RSTA Figure 80 Data Reception Procedures Data Sheet Description of Functional Blocks START Receive Y Message End RME ? N Receive Pool Full ...
Page 151
Figure 81 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) are received. The FIFO threshold (block size) is set to 32 byte in this ...
Page 152
Receive Frame Structure The management of the received HDLC frames as affected by the different operating modes (see Chapter 3.9.1) is shown in MDS2 MDS1 MDS0 MODE Non Auto/ Non Auto ...
Page 153
The IPAC-X indicates to the host that a new data block can be read from the RFIFOx by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFOx and information about the received frame is ...
Page 154
Data Transmission 3.9.3.1 Structure and Control of the Transmit FIFO The cyclic transmit FIFO buffers with a length of 64-byte for D-channel and 128 byte for each of the two B-channels have variable FIFO block sizes (thresholds) of • ...
Page 155
XRES, but have to be cleared by reading these interutps. Optionally two additional status conditions can be read by the host: – XDOV (Transmit Data Overflow), indicating that the data block ...
Page 156
With a 32 bytes block size (D- or B-channel) the XPR is initiated when a transmit FIFO space of at least 32 bytes is available ...
Page 157
Command XTF Figure 83 Data Transmission Procedure Data Sheet Description of Functional Blocks START Transmit N Pool Ready XPR ? Y Write one data block to XFIFO End of N Message ? Y Command XTF+XME End 157 IPAC-X PSB/PSF 21150 ...
Page 158
The following description gives an example for the transmission byte frame with a selected block size of 32 byte: • The host writes 32 bytes to the XFIFOx, issues an XTF command and waits for an XPR ...
Page 159
Transmit Frame Structure The transmission of transparent frames (XTF command) is shown in For transparent frames, the whole frame including address and control field must be written to the XFIFOx. The host configures whether the CRC is generated and ...
Page 160
Transmitter The transmitter sends the data out of the FIFO without manipulation. Transmission is always IOM-2 frame aligned and byte aligned, i.e. transmission starts in the first selected channel (B1, B2, D, according to the setting of register DCI_CR or ...
Page 161
HDLC Controller Interrupts The cause of an interrupt related to the HDLC controllers is indicated in the ISTA register by the ICD bit for D-channel, ICA for B-channel A and ICB for B-channel B. These bits point to the ...
Page 162
Test Functions The IPAC-X provides test and diagnostic functions for the S-interface, the D-channel and each of the two B-channels: • Digital loop via TLP (Test Loop, TMD and TMB registers) command bit The TX path of layer 2 ...
Page 163
Loop at the analog end of the S interface LT-T mode Test loop 3 is activated with the C/I channel command Activate Request Loop (ARL interface is not required since INFO3 is looped back internally ...
Page 164
Detailed Register Description The register mapping of the IPAC-X is shown in FFh 90h 80h 70h 60h 40h 30h 00h Figure 88 Register Mapping of the IPAC-X The register address range from 00 and the C/I-channel handler. The register ...
Page 165
The address range from 40 timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver data (TR), Monitor data (MON), HDLC/CI data (HCI) and controller access data (CDA), serial data strobe signal (SDS), IOM interface (IOM) ...
Page 166
SAP2 RBCLD RBC7 RBCHD 0 0 TEI1 TEI2 RSTAD VFR RDO TMD 0 0 CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 Transceiver, Auxiliary Interface NAME TR_ DIS_ BUS CONF0 TR TR_ 0 RPLL_ CONF1 ADJ TR_ DIS_ PDS ...
Page 167
Transceiver, Auxiliary Interface NAME SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 SQXR2 SQX21SQX22SQX23SQX24SQX31 SQX32SQX33 SQX34 SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 SQXR3 SQX41SQX42SQX43SQX44SQX51 SQX52SQX53 SQX54 ISTATR 0 x MASKTR 1 1 TR_ 0 0 MODE ACFG1 OD7 OD6 ACFG2 A7SEL A5SEL FBS A4SEL ACL AOE OE7 ...
Page 168
CDA_ DPS 0 0 TSDP11 CDA_ DPS 0 0 TSDP20 CDA_ DPS 0 0 TSDP21 BCHA_ DPS 0 0 TSDP_ BC1 BCHA_ DPS 0 0 TSDP_ BC2 BCHB_ DPS 0 0 TSDP_ BC1 BCHB_ DPS 0 0 TSDP_ BC2 TR_ ...
Page 169
TR_CR EN_ EN_ D B2R (CI_CS=0) TRC_CR 0 0 (CI_CS=1) BCHA_ DPS_ BCHB_ DPS_ DCI_CR DPS_ EN_ CI1 CI1 (CI_CS=0) DCIC_CR 0 0 (CI_CS=1) MON_CR DPS EN_ MON SDS1_CR ENS_ ENS_ TSS TSS+1 SDS2_CR ...
Page 170
MOX MOSR MDR MER MDA MOCR MRE MRC MSTA 0 0 MCONF 0 0 Interrupt, General Configuration Registers NAME ISTA ICA ICB MASK ICA ICB AUXI 0 0 AUXM 1 1 MODE1 0 0 MODE2 0 0 ...
Page 171
MASKB RME RPF STARB XDOV XFW CMDRB RMC RRES MODEB MDS2 MDS1 MDS0 EXMB XFBS RFBS RAH1 RAH2 RBCLB RBC7 RBCHB 0 0 RAL1 RAL2 RSTAB VFR RDO TMB 0 0 RFIFOB XFIFOB Data Sheet RFO XPR 1 XDU 0 ...
Page 172
D-channel HDLC Control and C/I Registers 4.1.1 RFIFOD - Receive FIFO D-Channel 7 RFIFOD A read access to any address within the range 00h-1Fh gives access to the “current” FIFO location selected by an internal pointer which is automatically ...
Page 173
RME ... Receive Message End One complete frame of length less than or equal to the defined block size (EXMD1.RFBS) or the last part of a frame of length greater than the defined block size has been received. The contents ...
Page 174
If an XDU interrupt occurs the transmit FIFO is locked until the XDU interrupt is read by the host (interrupt cannot be read if masked in MASKD). 4.1.4 MASKD - Mask Register D-Channel Value after reset MASKD ...
Page 175
XACI ... Transmitter Active Indication The D-channel HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The XACI-bit is active when an XTF-command is issued and the frame has not been completely transmitted 4.1.6 CMDRD - Command ...
Page 176
XRES ... Transmitter Reset The D-channel HDLC transmitter is reset and the XFIFOD is cleared of any data. This command can be used by the microcontroller to abort a frame currently in transmission. Note: After an XPR interrupt further data ...
Page 177
MDS2-0 Mode Number of Address Bytes Transparent – mode Transparent > 1 mode Transparent > 1 mode 2 Note: SAP1, SAP2: two programmable address values for the first received ...
Page 178
DIM2 DIM1 DIM0 Characteristics 0 0 Transparent D-channel, the collission detection is disabled 0 1 Stop/go bit evaluated for D-channel access handling 0 0 Last octet of IOM channel 2 used for TIC bus access 0 1 TIC bus access ...
Page 179
XCRC … Transmit CRC 0 … CRC is transmitted 1 … CRC isn’t transmitted RCRC… Receive CRC 0 … CRC isn’t stored in the RFIFOD 1 … CRC is stored in the RFIFOD ITF… Interframe Time Fill Selects the inter-frame ...
Page 180
SAP1 - SAPI1 Register Value after reset SAP1 SAPI1 ... SAPI1 value Value of the first programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD protocol. MHA... Mask High Address 0 … The SAPI ...
Page 181
RBCLD - Receive Frame Byte Count Low D-Channel Value after reset RBCLD RBC7 RBC7-0 ... Receive Byte Count Eight least significant bits of the total number of bytes in a received message (see RBCHD register). 4.1.13 ...
Page 182
TEI1 ... Terminal Endpoint Identifier In all message transfer modes except in transparent modes 0, 1 and extended transparent mode, TEI1 is used by the IPAC-X for address recognition. In the case of a two-byte address field, it contains the ...
Page 183
VFR... Valid Frame Determines whether a valid frame has been received. The frame is valid (1) or invalid (0). A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort). RDO ...
Page 184
MDS2-0 SA1 010 x (Non-Auto/8 x Mode) 011 0 (Non-Auto/16 0 Mode 111 0 (Transparent 0 Mode1) 1 101 - (Transparent - Mode 2) 1 Note: If SAP1 and SAP2 contain identical values, the combination SAP1,2-TEIG ...
Page 185
TLP ... Test Loop The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming from the layer 1 controller will not be forwarded to the layer 2 controller. The setting of TLP is only ...
Page 186
CIR0 is not read, only the first and the last C/I code is made available in CIR0 at the first and second read of that register, respectively. 4.1.19 CIX0 - Command/Indication Transmit 0 Value after reset CIX0 ...
Page 187
CODR1 ... C/I-Code 1 Receive CICW, CI1E ... C/I-Channel Width, C/I-Channel 1 Interrupt Enable These two bits contain the read back values from CIX1 register (see below). 4.1.21 CIX1 - Command/Indication Transmit 1 Value after reset CIX1 ...
Page 188
Transceiver Registers 4.2.1 TR_CONF0 - Transceiver Configuration Register 0 Value after reset TR_ DIS_ BUS CONF0 TR DIS_TR ... Disable Transceiver Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver again, a ...
Page 189
Note: The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’. For general information please refer to LDD ... Level Detection Discard 0: Automatic clock generation after detection of any signal on the line ...
Page 190
TR_CONF2 - Transmitter Configuration Register 2 Value after reset TR_ DIS_ PDS CONF2 TX DIS_TX ... Disable Line Driver 0: Transmitter is enabled 1: Transmitter is disabled For general information please refer to PDS ... Phase ...
Page 191
Outside the active window of SGO (defined in SGD) the level on pin SGO remains in the “stop”-state depending on the selected polarity (SGP), i.e. SGO=1 (if SGP=0) or SGO=0 (if SGP=1) outside the active window. 4.2.4 TR_STA - Transceiver ...
Page 192
TR_CMD - Transceiver Command Register Value after reset TR_ XINF CMD Important: This register is only writable if the Layer 1 state machine of the IPAC-X is disabled (TR_CONF0.L1SW = 1)! With the IPAC layer 1 ...
Page 193
LP_A ... Loop Analog The setting of this bit corresponds to the C/I command ARL. 0: Analog loop is open 1: Analog loop is closed internally or externally according to the EXLP bit in the TR_CONF0 register For general information ...
Page 194
SQXR1- S/Q-Channel TX Register 1 Value after reset SQXR1 0 MFEN MFEN ... Multiframe Enable Used to enable or disable the multiframe structure (see 0: S/T multiframe is disabled 1: S/T multiframe is enabled Readback value ...
Page 195
SQXR2 - S/Q-Channel TX Register 2 Value after reset SQXR2 SQX21 SQX22 SQX23 SQX24 SQX31 SQX32 SQX33 SQX34 SQX21-24, SQX31-34... Transmitted S Bits (NT mode only) Transmitted S bits in frames and 17 ...
Page 196
ISTATR - Interrupt Status Register Transceiver Value after reset ISTATR x x For all interrupts in the ISTATR register the following logical states are defined: 0: Interrupt is not acitvated 1: Interrupt is acitvated x ... ...
Page 197
MASKTR - Mask Transceiver Interrupt Value after reset MASKTR 1 1 The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1). 4.2.14 TR_MODE - Transceiver Mode Register 1 Value after reset: 000000xx ...
Page 198
Auxiliary Interface Registers 4.3.1 ACFG1 - Auxiliary Configuration Register 1 Value after reset ACFG1 OD7 OD6 For general information please refer to OD7-0 ... Output Driver Select for AUX7 - AUX0 0: output is open drain ...
Page 199
AUX5 provides an FSC or BCL signal output (FBOUT) which is selected in ACFG2.FBS. Bit AOE.OE5 is don’t care, the output characteristic (push pull or open drain) can be selected via ACFG1.OD5. For general information please refer to ...
Page 200
Note: An interrupt is only generated if the corresponding mask bit in AUXM is reset. This configuration is only valid if the corresponding output enable bit in AOE is disabled. For general information please refer to 4.3.3 AOE - Auxiliary ...