PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 220

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MASK
AUXI
4.5.2
Value after reset: FF
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the ISTA register can selectively be masked/disabled by setting
the corresponding bit in MASK to ’1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
4.5.3
Value after reset: 00
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
EAW ... External Awake Interrupt
An interrupt from the EAW pin has been detected.
WOV ... Watchdog Timer Overflow
Signals the expiration of the watchdog timer, which means that the microcontroller has
failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the
correct manner. A reset pulse has been generated by the IPAC-X.
TIN2, 1 ... Timer Interrupt 1, 2
An interrupt originated from timer 1 or timer 2 is recognized, i.e the timer has expired.
Data Sheet
mask bit in MASK is set, but no interrupt is generated.
7
7
MASK - Mask Register
AUXI - Auxiliary Interrupt Status Register
ICA
0
ICB
H
H
0
EAW
ST
WOV
CIC
220
TIN2
AUX
TRAN MOS
TIN1
Detailed Register Description
INT1
0
0
INT0
ICD
PSB/PSF 21150
2003-01-30
IPAC-X
WR (60)
RD (61)