PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 39

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.2.2
The 8-bit parallel microcontroller interface with address decoding on chip allows easy
and fast microcontroller access.
The parallel interface of the IPAC-X provides three types of m P buses which are selected
via pin ALE. The bus operation modes with corresponding pins are listed in
Table 5
(1)
(2)
(3)
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Note: If the multiplexed address/data bus type (3) is selected, the unused address pins
A read/write access to the IPAC-X registers can be done in multiplexed or non-
multiplexed mode:
• In non-multiplexed mode the register address must be applied to the address bus (A0-
• In multiplexed mode the address on the address/data bus (AD0-AD7) is latched in by
The IPAC-X provides two different ways to address the register contents which is
selected with the AMOD pin (’0’ = direct mode, ’1’ = indirect mode).
both register addressing modes.
Direct address mode (AMOD = ’0’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’1’): Only the LSB of the address is used to select
either the address register (A0 = ’0’) or the data register (A0 = ’1’). The microcontroller
writes the register address to the ADDRESS register before it reads/writes data from/to
the corresponding DATA register.
In indirect address mode the IPAC-X evaluates no address line except the least
significant address bit. The remaining address lines must not be left open but have to be
tied to logical ’1’.
Data Sheet
A7) for the data access via the data bus (AD0-AD7).
ALE before a data read/write access via the same bus is performed.
A0-A7 must be tied to V
Bus Mode
Motorola
Siemens/Intel non-multiplexed
Siemens/Intel multiplexed
Parallel Microcontroller Interface
Bus Operation Modes
DD
.
39
Pin ALE
V
V
Edge
DD
SS
Description of Functional Blocks
Control Pins
CS, R/W, DS
CS, WR, RD
CS, WR, RD, ALE
Figure 10
PSB/PSF 21150
Table
2003-01-30
illustrates
IPAC-X
5.