PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 223

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MODE2
For general information please refer to
RSS2, RSS1... Reset Source Selection 2,1
The IPAC-X reset sources for the RSTO output pin can be selected according to the
table below.
Bit 1
0
0
1
1
• If RSS = ’00’ no above listed reset source is selected and therefore no reset is
• Watchdog Timer
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
After a reset pulse generated by the IPAC-X and the corresponding interrupt (WOV or
CIC) the actual reset source can be read from the ISTA.
4.5.6
Value after reset: 00
Data Sheet
generated at RSTO.
After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started.
During every time period of 128 ms the microcontroller has to program the WTC1 and
WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits)
otherwise the watchdog timer expires and a reset pulse of 125 µs £ t £ 250 µs is
generated. Deactivation of the watchdog timer is only possible with a hardware reset.
125 µs £ t £ 250 µs at the RSTO pin:
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
7
MODE2 - Mode2 Register
0
RSS
Bit 0
0
1
0
1
H
0
0
C/I Code
Change
--
(reserved)
x
--
0
Chapter
223
INT_
POL
3.3.9.
EAW
--
x
--
0
Detailed Register Description
0
0
PPSDX RD/WR (63)
PSB/PSF 21150
Watchdog
Timer
--
--
x
2003-01-30
IPAC-X