PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 33

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3
3.1
Figure 7
• S/T-interface transceiver
• Serial or parallel microcontroller interface
• Two B-channel HDLC-controller with 128 byte FlFOs per channel and per direction
• One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable
• IOM-2 interface for terminal (TE mode), linecard (LT-T or LT-S) or NT applications
• D-channel access mechanism in all modes
• D-channel priority handler on IOM-2 for intelligent NT applications
• C/I- and Monitor channel handler
• Auxiliary interface with interrupt and general purpose I/O lines and LED drivers
• Clock and timing generation
• Digital PLL to synchronize the transceiver to the S/T interface
• Reset generation (watchdog timer)
The functional blocks are described in the following chapters.
Figure 7
Data Sheet
with programmable FIFO block size (threshold)
FIFO block size (threshold)
I/O- and
Interrupt
Lines
shows the architecture of the IPAC-X containing the following functions:
Description of Functional Blocks
General Functions and Device Architecture
Functional Block Diagram of the IPAC-X
Interface
Auxiliary
8-bit parallel
B-channel
RX/TX
HDLC
FIFOs
B-channel
RX/TX
HDLC
FIFOs
Peripheral Devices
Host Interface
IOM-2 Interface
IOM-2 Handler
Host
33
SCI
D-channel
RX/TX
FIFOs
HDLC
Handler
Description of Functional Blocks
MON
Reset
Interrupt
-generation
TIC
C/I
S Transceiver
DPLL
PSB/PSF 21150
21150_18
OSC
2003-01-30
IPAC-X