PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 175

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

IPAC-X
PSB/PSF 21150
Detailed Register Description
XACI ... Transmitter Active Indication
The D-channel HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The
XACI-bit is active when an XTF-command is issued and the frame has not been
completely transmitted
4.1.6
CMDRD - Command Register D-Channel
Value after reset: 00
H
7
0
CMDRD
RMC RRES
0
STI
XTF
0
XME XRES
WR (21)
RMC ... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFOD may be released.
RRES ... Receiver Reset
HDLC receiver is reset, the RFIFOD is cleared of any data.
STI ... Start Timer 1
The IPAC-X timer 1 is started when STI is set to one. The timer is stopped by writing to
the TIMR1 register.
Note: Timer 2 is controlled by the TIMR2 register only.
XTF ... Transmit Transparent Frame
After having written up to 16 or 32 bytes (EXMD1.XFBS) to the XFIFOD, the
microcontroller initiates the transmission of a transparent frame by setting this bit to ’1’.
The opening flag is automatically added to the message by the IPAC-X (except in the
extended transparent mode where no flags are used).
XME ... Transmit Message End
By setting this bit to ’1’ the microcontroller indicates that the data block written last to the
XFIFOD completes the corresponding frame. The IPAC-X terminates the transmission
by appending the CRC (if EXMD1.XCRC=0) and the closing flag sequence to the data
(except in the extended transparent mode where no such framing is used).
Data Sheet
175
2003-01-30