PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 57

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.3.4
TE Mode
In the state F7 (Activated) or if the internal layer-1 state machine is disabled and XINF
of register TR_CMD is programmed to ’011’ the B1, B2, D and E bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary or if the internal layer-1 statemachine is
disabled, bit TDDIS of register TR_CMD has additionally to be programmed to ’0’.
Figure 25
versa.
For the D channel the delay from the IOM-2 to the S/T interface is only valid if S/G
evaluation is disabled (MODED:DIM0=0). If S/G evaluation is enabled
(MODED.DIM2-0=0x1) the delay depends on the selected priority and the relation
between the echo bits on S and the D channel bits on the IOM-2, e.g. for priority 8 the
timing relation between the 8th D-bit on S bus and the D-channel on IOM-2.
Figure 25
Data Sheet
NT -> TE
TE -> NT
FSC
DU
DD
B1
B1
shows the data delay between the IOM-2 and the S/T interface and vice
Data Transfer and Delay between IOM-2 and S/T
F
B2 D
B2 D
F
Data Delay Between IOM-2 and S/T Interface Transparent Mode
(TE mode only)
B1
B1
E
D
D
B2
E
B2
E
B1
B1
B2 D
D
B2 D
D
B1
B1
E
D
D
B2
B2
E
E
57
B1
B1
D
F
D
B2 D
F
B2 D
B1
B1
E
Description of Functional Blocks
D
D
B2
E
B2
E
B1
B1
B2 D
B2 D
D
D
B1
B1
E
PSB/PSF 21150
D
D
B2
B2
E
E
2003-01-30
line_iom_s.vsd
IPAC-X
D
D