PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 110

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

timeslots can be configured, i.e. during each FSC frame the HDLC/FIFO will access
2 bit, 8 bit, 10 bit, 16 bit or 18 bit.
Some examples for access to IOM timeslots are given in
• Example 1 shows 18-bit access to B1 + B2 + D
• Example 2 shows 10-bit access to B2 + D
• Example 3 shows 10-bit access to B1 + D in channel 1
• Example 4 shows 16-bit access to MON0 + MON1.
.
Figure 60
The following registers are used to configure one of the two B-channel HDLC controllers
(channel A or B) for that (x = A or B):
• BCHx_TSDP_BC1 consists of bits for timeslot selection (TSS) and data port selection
• BCHx_TSDP_BC2 consists of bits for timeslot selection (TSS) and data port selection
• BCHx_CR consists of bits for channel selection (CS2-0) and data port selection
Data Sheet
(DPS) to program the first 8-bit timeslot.
(DPS) to program the second 8-bit timeslot.
(DPS_D) to program the 2-bit timeslot. Another 3 bits are used to selectively enable/
disable the first 8-bit timeslot (EN_BC1), the second 8-bit timeslot (EN_BC2) and the
2-bit timeslot (EN_D).
FSC
DU/DD
HDLC Controller access:
Example 1
Example 2
Example 3
Example 4
Examples for HDLC Controller Access
B1
B2
Channel 0
D
110
Channel 1
Description of Functional Blocks
Figure
60:
Channel 2
PSB/PSF 21150
2003-01-30
21550_24
IPAC-X