PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 68

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

– The continuous pulses are of alternating polarity. 48 pulses are transmitted in each
3.4
Figure 37
7.68 MHz clock signal (f
(8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to
S is output at SCLK which can be used for DCL input.
An internal clock divider provides an FSC (ACFG2.FBS=0) or BCL (ACFG2.FBS=1)
output on pin AUX5/FBOUT derived from the DCL clock. The output can be enabled via
ACFG2.A5SEL=1.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see
Figure 37
Data Sheet
frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding
C/I command is SCP (Send Continuous Pulses).
XTAL
7.68 MHz
shows the clock system of the IPAC-X. The oscillator is used to generate a
Clock Generation
OSC
Clock System of the IPAC-X
f
XTAL
XTAL
DPLL
). In TE mode the DPLL generates the IOM-2 clocks FSC
Chapter
Reset
Generation
SW Reset
C/I
EAW
Watchdog
ACFG2.FBS
68
3.2.4).
ACFG2.A5SEL
Description of Functional Blocks
FSC (TE mode)
DCL (TE mode)
BCL (TE mode)
SCLK (LT-T mode)
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
FBOUT (FSC/BCL output)
PSB/PSF 21150
2003-01-30
21150_06
IPAC-X