TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 215

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

Command/Status Register
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Bits
5:3
8
7
6
2
1
0
Reserved
Reserved
MEMSP
MSTR
Name
SERR
PERR
IOSP
DPE (Data Parity Error): This bit is set whenever a parity error is detected, even if the
parity error response is disabled (see bit PERR in the
cleared by writing it to 1 - writing a 0 has no effect.
SIGSE (Signaled System Error): This bit is set whenever the Tsi148 asserts SERR_. The
register is cleared by writing it to 1 while writing a 0 has no effect.
RCVMA (Received Master Abort): This bit is set when a master transaction (except for
Special Cycles) is terminated by a master-abort. It is cleared by writing it to 1; writing a 0 has
no effect.
RCVTA (Received Target Abort): This bit is set when a master transaction is terminated by
a target-abort. The register is cleared by writing it to 1 while writing a 0 has no effect.
SIGTA (Signalled Target Abort): The Tsi148 does not generate a target abort, therefore this
bit is hard-wired to a logic 0.
SELTIM (DEVSEL Timing): This field indicates that Tsi148 always asserts DEVSEL_ as a
medium responder.
DPED (Data Parity Error Detected): This bit is set when three conditions are met:
1. The Tsi148 asserted PERR_ itself or observed PERR_ asserted
2. The Tsi148 was the PCI/X Master for the transfer in which the error occurred
3. The PERR bit is set. This bit is cleared by writing it to 1; writing a 0 has no effect.
FAST (Fast Back-to-Back Capable): This bit indicates that the Tsi148 is capable of
accepting fast back-to-back transactions with different targets.
System Error Enable
N/A
Parity Error Response
N/A
Bus Master Enable
Memory Space Enable
I/O Space Enable
Function
Section 10.4.8 on page
Type
R/W
R/W
R/W
R/W
R
R
R
Reset
P/S/L
P/S/L
P/S/L
P/S/L
N/A
N/A
N/A
By
10. Registers > Register Map
Value
Reset
PCI
214). It is
0
0
0
0
0
0
0
PCI-X
Reset
Value
0
0
0
0
0
0
0
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