TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 224
TSI148-133CL
Manufacturer Part Number
TSI148-133CL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133CL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Package Type
BGA
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1906
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TSI148-133CL
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
TSI148-133CLY
Manufacturer:
TUNDRA
Quantity:
355
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10. Registers > Register Map
10.4.15
Table 48: Interrupt Line/Interrupt PIn/Minimum Grant/Maximum Latency Register
Interrupt Line/Interrupt PIn/Minimum Grant/Maximum Latency Register
224
Register Name: MXLA/MNGN/INTP/INTL
Reset Value: 0x
31:24
23:16
31:24
23:16
15:8
Bits
15:8
Bits
7:0
7:0
MNGN
MXLA
Name
INTL
INTP
Interrupt Line/interrupt PIn/Minimum Grant/Maximum Latency
Registers
MXLA (Maximum Latency): This is a read-only register from the PCI/X configuration
space, and may be written at any time from within the Combined Register Group. The MXLA
register specifies how often access to the PCI/X bus is required. The value is presented in
units of 0.25 us. This register defaults 0x00 following the release of reset which indicates that
there are no particular latency requirements.
MNGN (Minimum Grant): This is a read-only register from the PCI/X configuration space,
and may be written at any time from within the Combined Register Group. The MNGN
register specifies how long of a burst period is required. The value is presented in units of 0.25
us. This register defaults to 0x00 following the release of reset which indicates that there are
no particular grant requirements.
7
Maximum Latency
Minimum Grant
Interrupt Pin
Interrupt Line
6
5
Function
4
MNGN
MXLA
INTL
INTP
3
Register Offset: PCFS + 0x3C - CRG + 0x03C
Tsi148 PCI/X-to-VME Bus Bridge User Manual
PCFS
Space
Type
R/W
R
R
R
2
Table 49
Space
CRG
Type
R/W
R/W
R/W
see
1
80A3020_MA001_13
Reset
P/S/L
P/S/L
P/S/L
P/S/L
By
Value
Reset
0x00
0x00
0x01
0x00
0
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