TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 253

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
DLT (Deadlock Timer): These bits define the time the VME Slave waits after detecting a
potential deadlock before asserting the RETRYO_ signal.
Table 80: Deadlock Timer
NELBB (No Early Release of Bus Busy): When this bit is set, the Tsi148 asserts BBSYO_
whenever ASI_ is asserted. This disables the early release of bus busy function for all
VMEbus masters. This can sometimes help debug systems when noise is causing arbitration
problems.
a. A VCLK is a Tsi148 internal clock which is a
133 MHz clock.
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
DLT
The timer checks only for a potential deadlock. The deadlock condition it
monitors is when the Tsi148's PCI/X to VME write buffers are completely full and
a VMEbus initiator attempts a read to a PCI/X target through the Tsi148. This is
the only potential deadlock condition this timer monitors.
Deadlock Retry Disabled
16384 VCLKs
32768 VCLKs
1024 VCLKs
2048 VCLKs
4096 VCLKs
8192 VCLKs
128 VCLKs
256 VCLKs
512 VCLKs
16 VCLKs
32 VCLKs
64 VCLKs
Reserved
Reserved
Reserved
Time
a
10. Registers > Register Map
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