TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 96

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

4. DMA Interface > Overview DMA Controller
4.1
4.2
4.3
96
Overview DMA Controller
The Tsi148 has two independent, single channel DMA controllers that enable the transfer of
large blocks of data without processor intervention. Each DMA controller is programmed by a
set of registers that reside within the LCSR group (see
Each DMA controller supports 64-bit addressing on the VMEbus and the PCI/X bus. The
amount of data moved during a command is only limited by the 32-bit byte counter, allowing
transfer counts to range from 1 byte to 4 Gbytes.
Architecture
Each DMA controller connects to the Linkage Module and uses the PCI/X Master and VME
Master to transfer data. The core of the DMA controller is the DMA buffer - an 8 Kbyte
buffer. The buffer is used for all transactions regardless of the direction.
The DMA controllers have been optimized to transfer data over the PCI/X bus in multiple
cache-line bursts. All interactions with the VMEbus are handled by the VME Master. The
controllers transfer data using 32-bit or 64-bit burst transfers on the PCI/X bus and 16-bit,
32-bit, or 64-bit transfers on the VMEbus.
DMA Buffers
Each DMA controller has an 8 Kbyte buffer that is used to hold data transferred between the
source and destination bus. For example, if the transfer is from the PCI/X bus to the VMEbus,
the DMA controller requests data from the PCI/X Master and then sends it to the VME
Master.
The data moves from the PCI/X bus into the PCI/X Master’s read buffer data queue and then
through the Linkage Module to the buffer in the DMA controller. The data then moves from
the DMA buffer through the Linkage Module to the VME Master’s write buffer data queue.
The data is then transferred to the VMEbus.
The Combined Register Group (CRG) map decoder can be programmed to allow
access to the control registers from the VMEbus.
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Section 10.2.3 on page
80A3020_MA001_13
193).