TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 60

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

2. VME Interface > VME Master
2.3.5
2.3.6
60
VMEbus Exception Handling
When a VMEbus transfer initiated by the VME Master does not complete successfully, the
status is saved in the VMEbus exception registers. The exception registers are updated when a
transaction is terminated with a bus error, or a 2eVME or 2eSST transfer is terminated with a
slave termination.
The VMEbus exception registers include:
•
•
•
For more information on the VMEbus exception registers, refer to
page
When the VME Master encounters one of these conditions, any write data in the buffers is
removed (flushed). If the transaction was a VMEbus read, the VME Master completes the
Linkage Module command by filling the buffer with a data pattern of all ones.
If a second exception occurs before the software has acknowledged the first exception, the
status registers are not updated, however, the overflow bit is set to indicate that more than one
exception occurred.
Utility Functions
Tsi148 provides the following VMEbus utility functions:
•
•
•
VMEbus Exception Address Upper (VEAU)
VMEbus Exception Address Lower (VEAL)
VMEbus Exception Attributes (VEAT)
VMEbus Location Monitor which allows one VMEbus board to broadcast an interrupt to
multiple boards. The processor sends an interrupt by reading, or writing to, one of the
VMEbus monitored addresses. Other boards in the system monitor this address and
interrupt their processors when an access is detected. The monitored VMEbus addresses
are programmable and works in A16, A24, A32, and A64 VMEbus address space (see
Section 2.3.6.1 on page
Three registers are provided for this function: Location Monitor Base Address Upper
register (LMBAU), Location Monitor Base Address Lower register (LMBAL), and
Location Monitor Attribute register (LMAT) (see
Eight Semaphore registers for resource sharing (see
Four Mailbox registers used to provide a communication path between the VMEbus and
PCI/X Logic (see
265).
The interrupt controller can be programmed to generate an interrupt when the
exception registers are updated.
Section 2.3.6.3 on page
61).
63).
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Section 10.4.62 on page
Section 2.3.6.2 on page
Section 10.4.38 on
80A3020_MA001_13
298).
62).