TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 83

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3.3.1.2
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Transaction Mapping
The PCI-X bus is capable of many different transaction types, including: single beat
transactions, burst transactions, each with flexible byte enable patterns. These transactions
must be mapped to corresponding transactions on the VMEbus. There are many different
modes and protocols supported by the VMEbus and the numerous programmable options.
The following rules can be applied to transactions:
•
•
PCI-X-to-VME Address Mapping
The PCI-X Target has eight programmable PCI-X bus target images which map PCI-X
transactions to VME address space.
The PCI-X Target maps a PCI-X address to the destination address space using eight
programmable target images. These target images provide windows into the VMEbus from
the PCI-X bus. The PCI-X address is compared with the address range of each target image,
and if the address falls within the specified range, the offset is added to the incoming address
to form the destination address.
Writes
— During a PCI-X bus write, the selected bytes on the PCI-X bus map directly to the
— During a PCI-X bus memory write block, the number of bytes in the byte count,
Reads
— The PCI-X bus protocol includes a byte count. The number of bytes requested from
— The PCI-X Target does not merge, combine, or gather transactions. Because of the
destination bus. The Tsi148 does not write to bytes on the destination bus that are not
selected on the PCI-X bus.
along with the starting address map directly to the destination bus.
the destination bus generally matches the byte count requested by the PCI-X bus
master.
different bus widths, a single beat transaction on the PCI-X bus may map to a multi
beat transaction on the destination bus. A transaction that completes in a single bus
tenure on the PCI-X bus may not complete in a single bus tenure on the destination
bus.
Any locations with read sensitive bits should be accessed using a byte read or a
read that matches the width of the location (preferably the memory read DWORD
command). There is a one-to-one correspondence between the bytes written on the
PCI-X bus and bytes written on the destination bus.
3. PCI/X Interface > PCI-X Mode
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