TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 79

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
PCI Master
The PCI Master provides the interface between Linkage Module and the PCI bus. The PCI
Master supports a 32-bit and 64-bit data bus and 32-bit and 64-bit addresses.
PCI Master Commands
The PCI Master can generate the following PCI bus commands:
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PCI Master Buffers
The PCI Master has one read buffer and one write buffer. The buffers are segmented into two
parts: a data queue and a command queue. Both the read and write buffer command queues
are six entries deep. The read buffer data queue is 512 byte while the write data buffer is
4 Kbyte.
The read buffer stores Linkage Module commands when servicing a read request from the
VMEbus to the PCI bus. The PCI Master requests the PCI bus when it receives a read
command from the Linkage Module. After the read transaction has been satisfied on the PCI
bus, and the PCI read buffer data queue has the requested data, the PCI Master transfers the
data through the Linkage Module to the VMEbus.
The write buffer stores Linkage Module commands and data. The PCI Master requests the
PCI bus when it receives write data from the Linkage Module. The write buffer is considered
full when either the command queue or data queue is full.
PCI Master Bandwidth Control
The PCI bus latency timer can be used to control the PCI bus bandwidth used by Tsi148. The
PCI Master requests the PCI bus when it has a transaction to complete (for example, when the
PCI Master receives a command from the Linkage Module or when the master needs to
complete a previously received command). The PCI Master maintains mastership of the PCI
bus until the Linkage Module command is completed or until the PCI bus grant is removed
and the latency timer has expired.
Memory read: A memory read command is used when the requested byte count is less
than or equal to 4 bytes.
Memory read multiple: The memory read multiple command is used when the requested
byte count is greater than 32 bytes.
Memory read line: A memory read line command is used when the requested byte count
is greater than 4 bytes and less than or equal to 32 bytes.
Memory write
Dual address cycle: A dual address cycle is generated when the PCI address is greater
than 32-bits.
3. PCI/X Interface > PCI Mode
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