TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 56

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

2. VME Interface > VME Master
2.3.2
2.3.3
56
Table 1: VMEbus Address Mode Codes
There are four user defined AM codes. When the user defined AM codes are used, the AM[1]
bit is defined by the VMEbus Supervisory Mode (SUP) bit and the AM[0] bit is defined by
the VMEbus Program Mode (PGM) bit in the Outbound Translation Attribute register (see
Section 10.4.26 on page
VME Master Buffers
The VME Master interfaces to the Linkage Module through separate read and write buffers.
The VME Master has two write buffers and two read buffers.
The read buffers are each segmented into two parts: the data queue and the command queue.
The read buffers are used to store data received from the VMEbus. The data queue can accept
up to 4 Kbytes of data. The command queue stores a single entry. The two read buffers allows
the Tsi148 to perform back-to-back reads from the VMEbus.
The write buffers are each segmented into two parts: the data queue and the command queue.
The data queue can have up to 4 Kbytes of data. The command queue can accept one entry.
The write buffers are used to receive writes from the Linkage Module. The two write buffers
allow the VME Master to accept two Linkage Module commands. The two write buffers
allows the Tsi148 to perform back-to-back writes from the VMEbus.
VME Master Read-Modify Write (RMW) Cycles
A RMW cycle allows the VME Master to read from a VMEbus slave and then write to the
same resource without relinquishing bus tenure between the two operations. RMW cycles can
be generated by the Tsi148 VME Master. The VME Master generates RMW cycles on 8, 16,
and 32-bit aligned transfers. For more information on the VME RMW registers, refer to
Section 10.4.29 on page
The following registers are used when the RMW functionality is enabled
•
The VMEbus RMW Address Upper (RMWAU) and VMEbus RMW Address Lower
(RMWAL) registers: These registers specify the PCI/X address, both the upper bits
(63:32) and lower bits (31:2), for the RMW cycle.
AMODE
0x1101
0x1110
0x1111
245.
239) .
Address Mode
Reserved
Reserved
Reserved
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13