PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 110

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

3.8.2
3.8.2.1
The cyclic receive FIFO buffer with a length of 64 byte has a variable FIFO block size
(threshold) of 4, 8, 16 or 32 bytes which can be selected by setting the corresponding
RFBS bits in the EXMD register. The variable block size allows an optimized HDLC
processing concerning frame length, I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block oriented with the
microcontroller as master. The control of the data transfer between the CPU and the
ISAC-SX TE is handled via interrupts (ISAC-SX TE
ISAC-SX TE).
There are three different interrupt indications in the ISTAD registes concerned with the
reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
– RME (Receive Message End) interrupt, indicating that the reception of one message
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
There are two control commands that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the ISAC-SX TE that a data
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
Note: The significant interrupts and commands are underlined as only these are
Data Sheet
(EXMD.RFBS) can be read from RFIFOD. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
is completed, i.e. either
• a short message is received
(message length
• the last part of a long message is received
(message length
and is stored in the RFIFOx.
be stored in RFIFOD and is therefore lost as the RFIFOD is occupied. This occurs if
the host fails to respond quickly enough to RPF/RME interrupts since previous data
was not read by the host.
block has been read from the RFIFOD and the corresponding FIFO space can be
released for new receive data.
receive FIFO of any data (e.g. used before start of reception). It has to be used after
a change of the message transfer mode. Pending interrupt indications of the receiver
are not cleared by RRES, but have to be cleared by reading these interrupts.
commonly used during a normal reception sequence.
Data Reception
Structure and Control of the Receive FIFO
the defined block size (EXMD.RFBS)) or
the defined block size (EXMD.RFBS))
110
Description of Functional Blocks
Host) and commands (Host
PSB 3186
PSF 3186
2000-08-23