PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 98

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

3.7.3.6
Figure 51
Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt
Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of Reception
MER, MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort
MAB interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE prevents the occurrence of MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is
generated only for the first byte of a receive packet. When both MRE and MRC are
active, MDR is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored. (Additionally, an active MRC enables the control of the
MR handshake bit according to the MONITOR channel protocol.)
Figure 51
Data Sheet
shows the MONITOR interrupt structure of the ISAC-SX TE. The MONITOR
MONITOR Interrupt Logic
TRAN
MASK
WOV
MOS
ICD
ST
CIC
Interrupt
MONITOR Interrupt Structure
TRAN
ISTA
WOV
MOS
ICD
ST
CIC
98
Description of Functional Blocks
MOCR
MRE
MIE
MOSR
MER
MDR
MDA
MAB
PSB 3186
PSF 3186
2000-08-23