PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 47

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

PSB 3186
PSF 3186
Description of Functional Blocks
After multiframe synchronization has been established, the Q data will be inserted at the
upstream (TE
NT) F
bit position in each 5th S/T frame (see
Table
8).
A
When synchronization is not achieved or lost, each received F
bit is mirrored to the next
A
transmitted F
bit.
A
Multiframe synchronization is achieved after two complete multiframes have been
detected with reference to F
/N bit and M bit positions. Multiframe synchronization is lost
A
if bit errors in F
/N bit or M bit positions have been detected in two consecutive
A
multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR1).
The multiframe synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR1).
Interrupt Handling for Multiframing
To trigger the microcontroller for a multiframe access an interrupt can be generated once
per multiframe (SQW) or if the received S-channels have changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
Data Sheet
47
2000-08-23