PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 151

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

4.2
4.2.1
Value after reset: 01
TR_
CONF0
DIS_TR ... Disable Transceiver
Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver
again, a transceiver reset must be issued (SRES.RES_TR = 1). The transceiver must
not be reenabled by setting DIS_TR from “1” to “0”.
For general information please refer to
EN_ICV ... Enable Illegal Code Violation
0: normal operation
1: ICV enabled. The receipt of at least one illegal code violation within one multi-frame
is indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames.
EXLP ... External loop
In case the analog loopback is activated with C/I = ARL the loop is a
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/SX2
Note: The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
For general information please refer to
LDD ... Level Detection Discard
0: Automatic clock generation after detection of any signal on the line in
power down state
1: No clock generation after detection of any signal on the line in power down state
Note: If an interrupt by the level detect circuitry is generated, the microcontroller has to
For general information please refer to
Data Sheet
set this bit to ’0’ for an activation of the S/T interface.
7
Transceiver Registers
TR_CONF0 - Transceiver Configuration Register 0
DIS_
TR
H
0
EN_
ICV
0
Chapter
Chapter
Chapter 3.3.8
151
0
3.3.9.
3.3.10.
0
and
Detailed Register Description
Chapter
EXLP
0
LDD
3.7.6.
RD/WR (30)
PSB 3186
PSF 3186
2000-08-23