PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 157

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PSB3186FV1.4

Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB3186FV1.4

Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
 Details
4.2.10
Value after reset: FF
MASKTR
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.2.11
Value after reset: 00
ACFG2
Note: Although no other Auxiliary Configuration Registers are supported by ISAC-SX
ACL ... ACL Function Select
0: Pin ACL automatically indicates the S-bus activation status by a LOW level.
1: The output state of ACL is programmable by the host in bit LED.
Note: An LED with preresistance my directly be connected to ACL.
LED ... LED Control
If enabled (ACL = 1) the LED with preresistance connected across VDD and ACL is
switched ...
0: ... OFF (high level on pin ACL)
1: ... ON (low level on pin ACL)
Data Sheet
TE, the name ACFG2 for this register was chosen intentionally in compliance with
ISAC-SX PEB3086.
7
7
MASKTR - Mask Transceiver Interrupt
ACFG2 - Auxiliary Configuration Register
1
0
H
H
1
0
1
0
1
0
157
ACL
LD
LED
RIC
Detailed Register Description
SQC
0
0
0
SQW
0
RD/WR (3D)
RD/WR (39)
PSB 3186
PSF 3186
2000-08-23

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