PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 39

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in
3.2.5
The ISAC-SX TE provides two timers which can be used for various purposes. Each of
them provides two modes
generated only once after expiration of the selected period, and a periodic timer interrupt,
which means an interrupt is generated continuously after every expiration of that period.
Table 7
Address
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from AUXI
(TIN1, TIN2) and each of the interrupt sources can be masked in AUXM.
Figure 10
Data Sheet
24
65
H
H
Timer Modes
Register
TIMR1
TIMR2
ISAC-SX TE Timers
Timer Interrupt Status Registers
TRAN
MASK
AUX
MOS
CIC
ICD
Interrupt
ST
Modes
Periodic
Count Down
Periodic
Count Down
(Table
TRAN
ISTA
AUX
MOS
CIC
ICD
ST
7), a count down timer interrupt, i.e. an interrupt is
39
Period
64 ... 2048 ms
64 ms ... 14.336 s
1 ... 63 ms
1 ... 63 ms
AUXM
TIN2
TIN1
EAW
WOV
Description of Functional Blocks
Figure
AUXI
TIN2
EAW
WOV
TIN1
9.
PSB 3186
PSF 3186
2000-08-23