ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 116

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
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Figure 56. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
but master and slave must be programmed with the same timing mode.
MOSI
MISO
SCK
SS
SOD
bit
Figure
SPIDR
57.
8-bit Shift Register
Read Buffer
SERIAL CLOCK
GENERATOR
CONTROL
MASTER
Doc ID 12321 Rev 5
Data/Address Bus
Read
Write
7
SPIE
SPIF WCOL
7
SPE
CONTROL
SPR2
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
Figure 60 on page
ST72344xx ST72345xx
CPOL
0
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
0
1
SPR0
121)
SSI
0
0