ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 25

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Table 4.
Address
003Ch
003Dh
004Ch
004Dh
005Ch
005Dh
003Ah
003Bh
003Eh
003Fh
004Ah
004Bh
004Eh
004Fh
005Ah
005Bh
005Eh
005Fh
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
Hardware register map (continued)
TIMER A
TIMER B
Block
SCI
I
2
C
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Register
label
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
Reserved area
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
I
I
I
I
I
I
I
2
2
2
2
2
2
2
C Control Register
C Status Register 1
C Status Register 2
C Clock Control Register
C Own Address Register 1
C Own Address Register2
C Data Register
Doc ID 12321 Rev 5
Reserved area (1 Byte)
Reserved area (1 byte)
Register name
Register and memory map
x000 0000b
status
Reset
FCh
FCh
FCh
FCh
FFh
FFh
FFh
FFh
C0h
00h
00h
80h
00h
80h
00h
00h
00h
80h
00h
80h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
40h
00h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
--
(1)
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
Remarks
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