ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 134

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
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Character transmission
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Idle characters
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In
this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and
the transmit shift register (see
Procedure:
–
–
–
–
Clearing the TDRE bit is always performed by the following software sequence:
a)
b)
The TDRE bit is set by hardware and it indicates:
–
–
–
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores
the data in the TDR register and which is copied in the shift register at the end of the
current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places
the data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the
TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the
CCR register.
Clearing the TC bit is performed by the following software sequence:
a)
b)
Setting the SBK bit loads the shift register with a break character. The break frame
length depends on the M bit (see
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing
this bit by software the SCI insert a logic 1 bit at the end of the last break frame to
guarantee the recognition of the start bit of the next frame.
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Select the M bit to define the word length.
Select the desired baud rate using the SCIBRR and the SCIETPR registers.
Set the TE bit to send an idle frame as first transmission.
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be
transmitted.
An access to the SCISR register
A write to the SCIDR register
The TDR register is empty.
The data transfer is beginning.
The next data can be written in the SCIDR register without overwriting the
previous data.
An access to the SCISR register
A write to the SCIDR register
Doc ID 12321 Rev 5
Figure
Figure
64).
64).
ST72344xx ST72345xx