ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 139

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Note:
Setting the RWU bit by software puts the SCI in sleep mode:
●
●
A muted receiver can be woken up in one of the following two ways:
●
●
A receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
A receiver wakes-up by Address Mark detection when it received a “1” as the most
significant bit of a word, thus indicating that the message is an address. The reception of
this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which
allows the receiver to receive this word normally and to use it as an address word.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in
Table 56.
1. SB: Start Bit, STB: Stop Bit, PB: Parity Bit.
In case of wakeup by an address mark, the MSB bit of the data is taken into account and not
the parity bit
Even parity: The parity bit is calculated to obtain an even number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain an odd number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte
has an even number of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if
odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR
register and an interrupt is generated if PIE is set in the SCICR1 register.
0
1
M bit
None of the reception status bits can be set.
All the receive interrupts are inhibited.
by Idle Line detection if the WAKE bit is reset,
by Address Mark detection if the WAKE bit is set.
Frame formats
0
1
0
1
PCE bit
Doc ID 12321 Rev 5
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
SCI frame
(1)
Table
On-chip peripherals
56.
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