ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 57
ST72344S4
Manufacturer Part Number
ST72344S4
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet
1.ST72344S4.pdf
(247 pages)
Specifications of ST72344S4
Up To 16 Kbytes Program Memory
single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
5 Power-saving Modes
Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
16-bit Timer A With
1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes
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ST72344xx ST72345xx
8.5
8.5.1
Figure 23. Nested interrupt management
Interrupt register description
CPU CC register interrupt bits
Reset value: 111x 1010 (xAh)
Bits 5, 3 = I1, I0 Software interrupt priority
These two bits indicate the current interrupt software priority.
Table 14.
1. TRAP and reset events can interrupt a level 3 program.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable
7
1
11 / 10
MAIN
RIM
Interrupt software priority
1
IT2
Priority
IT1
(1)
)
I1
IT4
Doc ID 12321 Rev 5
TRAP
IT4
H
Read/Write
IT0
IT3
Low
High
I0
IT1
Level
IT2
10
SOFTWARE
PRIORITY
LEVEL
N
MAIN
1
0
0
1
I1
3
3
2
1
3
3
3/0
Z
I1
0
1
0
1
1 1
1 1
0 0
0 1
1 1
1 1
Interrupts
I0
C
0
57/247
I0
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