ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 39

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
6.3.2
Note:
Stack pointer (SP)
Reset value: 01 FFh
The Stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack pointer (called S) can be directly accessed by a LD
instruction.
When the lower limit is exceeded, the Stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure
●
●
A subroutine call occupies two locations and an interrupt five locations in the stack area.
SP7
15
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
On return from interrupt, the SP is incremented and the context is popped from the
stack.
0
7
12.
SP6
0
SP5
0
Doc ID 12321 Rev 5
SP4
0
Read/Write
Read/Write
Figure
12).
SP3
0
SP2
0
Central processing unit
SP1
0
SP0
8
1
0
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