ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 65

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
9.2
Note:
9.3
Slow mode
This mode has two targets:
●
●
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (f
In this mode, the master clock frequency (f
and peripherals are clocked at this lower frequency (f
Slow-wait mode is activated by entering Wait mode while the device is in Slow mode.
Figure 26. Slow mode clock transitions
Wait mode
Wait mode places the MCU in a low-power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter
branches to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f
Figure
27.
CP1:0
f
SMS
CPU
f
OSC2
Doc ID 12321 Rev 5
f
OSC2
00
New slow
frequency
OSC2
request
CPU
/2
) to the available supply voltage.
) can be divided by 2, 4, 8 or 16. The CPU
01
CPU
f
OSC2
).
Normal Run mode
/4
request
f
OSC2
Power-saving modes
CPU
).
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