ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 137

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ST72344S4

Manufacturer Part Number
ST72344S4
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72344S4

Up To 16 Kbytes Program Memory
single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
5 Power-saving Modes
Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
16-bit Timer A With
1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes
ST72344xx ST72345xx
Framing error
Figure 65. SCI baud rate and extended prescaler block diagram
A framing error is detected when:
When the framing error is detected:
The FE bit is reset by a SCISR register read operation followed by a SCIDR register
read operation.
f
CPU
The stop bit is not recognized on reception at the expected time, following either a
de-synchronization or excessive noise.
A break is received.
the FE bit is set by hardware
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
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/PR
EXTENDED TRANSMITTER PRESCALER REGISTER
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCP1
CONVENTIONAL BAUD RATE GENERATOR
SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Doc ID 12321 Rev 5
TRANSMITTER RATE
EXTENDED PRESCALER
CONTROL
RECEIVER RATE
CONTROL
SCIBRR
SCIERPR
SCIETPR
On-chip peripherals
RECEIVER
TRANSMITTER
CLOCK
CLOCK
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