cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 172

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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Flash Controller Functional Description
Special considerations must be made for NOR Flash write
operations. Depending on the manufacturer and write
mode, each write can take from a few microseconds to a
few hundred microseconds. Specifically, the software per-
forming the write must observe the following procedure:
1)
2)
3)
The “wait” in step two is implemented using an appropriate
time base reference. There is no reference within the Flash
Controller subsystem.
Some NOR devices provide a ready line that de-asserts
during the “wait” in step two. Direct use of this signal is not
supported by the Flash Controller. The NOR write software
should use an appropriate time base reference to deter-
mine when the device is ready, that is, determine how long
to wait for the current write to complete before starting
another write. Alternatively, the NOR device internal status
may be read to determine when the write operation is com-
plete. Refer to NOR Flash manufactures data sheets for
additional write operation details.
ADD[9:0]
ALE
CS#
WE#, RE#
DATA (write)
DATA (read)
Write to device.
Wait an amount of time dependent on manufacturer’s
specifications.
Repeat from #1 until all writes are completed.
0
1
Higher Address
Higher Address
Higher Address
Address
Phase
2
Figure 4-57. NOR Flash Basic Timing
3
4
tS
tS
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Lower Address
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(Continued)
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4.18.3 Flash Controller Interface Timing Diagrams
4.18.3.1 NOR/GPCS
The NOR/GPCS timing has two phases: address phase
and data phase.
In the address phase, the address bus and data bus
present a higher address, ADD[27:10]. Board designers
can use external latches, such as 74x373, to latch the
address bits.
In the data phase, the address bus presents ADD[9:0], and
the data bus is for data read or write.
The Flash Controller is running off internal Local bus clock ,
which is at the highest frequency of 33 MHz. The address
phase is always two clock periods. The ALE signal asserts
high in the first-half clock period and de-asserts in the sec-
ond clock period. A 74LCX373 only needs 4 ns setup time
and 2 ns hold time (worst case). This timing provides a lot
of flexibility for the designing of the board. In the data
phase, the address bus and write data bus are available in
the first clock period. In the second clock period of the data
phase, chip select goes low. After the required hold time,
chip select goes high, and write data bus change. After one
Local bus clock from chip select change (going high),
address bus changes. The setup time, strobe pulse width,
and hold time are programmable through the NOR timing
registers. See Section 5.19.1.2 "NOR Flash Timing MSRs"
on page 504.
Figure 4-57 and Figure 4-58 provides some NOR Flash
timing examples.
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Data Phase
Y
Data
tP
Y+1
Data
Y+2
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tH
tH
Z
Z+1
Revision 0.8
Z+2