cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 325

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
PIT Register Descriptions
5.8.2
5.8.2.1
I/O Address
Type
Reset Value
5.8.2.2
I/O Address
Type
Reset Value
I/O Address 43h[7:0] = 1101xx10 or 0010xxxx
I/O Address 43h[7:0] = 11110xx10
Note: PIT_CNTR2_EN (PIT Counter 2 Enable) bit is located at I/O Address 61h[0] (see Section 5.8.2.8 "Port B Control
CNTR0_OUT
Bit
3:2
Bit
7:0
4
1
0
7
7
PIT Native Registers
(PIT_PORTBCTL)" on page 330).
PIT Timer 0 Counter - System (PIT_TMR0_CNTR_SYS)
PIT Timer 0 Status - System (PIT_TMR0_STS_SYS)
Name
PIT_CNTR_ACC_
DLY_EN
RSVD
PIT_CNTR1_EN
PIT_CNTR0_EN
Name
CNTR0
CNTR0_LOAD
40h
W
00h
40h
R
00h
6
6
Description
PIT Counter Access Delay Enable. Used as an access delay enable for the read and
write operations of the PIT counters. This bit introduces a 1 µs delay between succes-
sive reads and/or writes of the PIT counters. This bit is intended to ensure that older,
DOS-based programs that rely on the PIT timing access to be 1 µs still function prop-
erly.
0: Disable access delay.
1: Enable access delay.
Reserved. Read zero. Write “don’t care”.
PIT Counter 1 Enable.
0: Sets GATE1 input low.
1: Sets GATE1 input high.
PIT Counter 0 Enable.
0: Sets GATE0 input low.
1: Sets GATE0 input high.
Description
Counter 0 Value. Provides the base counter value.
PIT_CNTRL Bit Descriptions (Continued)
(Continued)
5
5
PIT_TMR0_CNTR_SYS Bit Description
PIT_TMR0_CNTR_SYS_ Register Map
CNTR0_RW
PIT_TMR0_STS_SYS Register Map
CNTR0_CUR_COUNT
4
4
CNTR0
325
3
3
CNTR0_MODE
2
2
1
1
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BCD
0
0