cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 342

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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PIC Register Descriptions
5.9.2.6
I/O Port
Type
Reset Value
5.9.2.7
I/O Port
Type
Reset Value
IRQ7_15M
Bit
7:5
3:2
Bit
4
1
0
7
6
5
4
3
2
1
0
7
7
Operation Command Word 1 / Interrupt Mask (PIC_OCW1/IMR)
Operation Command Word 2 (PIC_OCW2)
Name
RSVD
SPEC_NST
RSVD
AUTO_EOI
RSVD
Name
IRQ7_15M
IRQ6_14M
IRQ5_13M
IRQ4_12M
IRQ3_11M
IRQ2_10M
IRQ1_9M
IRQ0_8M
Master: 021h
Slave:
IRQ6_14M
Master: 020h
Slave:
ROT_EOI
6
6
0A1h
R/W
00h
0A0h
WO
00h
IRQ5_13M
Description
Reserved. Write to 0.
Reserved (Special Fully Nested Mode). Write to 0.
Reserved. Write to 0.
Auto End of Interrupt. This feature is present, but is not recommended for use. When
set to 1, this bit causes the PIC to automatically issue an End of Interrupt internally,
immediately after each Interrupt Acknowledge from the CPU. When cleared to 0 (the
default), it requires software action (writing to the OCW2 register) to signal End of Inter-
rupt.
0: Normal EOI.
1: Auto EOI (not recommended).
Reserved. Write to 1 (8086/8088 mode).
Description
IRQ7 / IRQ15 Mask. 0: Not Masked; 1: Masked.
IRQ6 / IRQ14 Mask. 0: Not Masked; 1: Masked.
IRQ5 / IRQ13 Mask. 0: Not Masked; 1: Masked.
IRQ4 / IRQ12 Mask. 0: Not Masked; 1: Masked.
IRQ3 / IRQ11 Mask. 0: Not Masked; 1: Masked.
IRQ2 / IRQ10 Mask. 0: Not Masked; 1: Masked.
IRQ1 / IRQ9 Mask. 0: Not Masked; 1: Masked.
IRQ0 / IRQ8 Mask. 0: Not Masked; 1: Masked.
5
5
(Continued)
PIC_OCW1/IMR Bit Descriptions
PIC_OCW1/IMR Register Map
PIC_ICW4 Bit Descriptions
PIC_OCW2 Register Map
IRQ4_12M
4
4
342
00
IRQ3_11M
3
3
IRQ2_10M
2
2
IRQ1_9M
IRQ
1
1
IRQ0_8M
Revision 0.8
0
0