cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 360

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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5.12 UART AND IR PORT REGISTER DESCRIPTIONS
The registers for the UART/IR Controller are divided into
three sets:
• Standard GeodeLink Device MSRs (Shared with DIVIL,
• UART/IR Controller Specific MSRs
• UART/IR Controller Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 3.2 "CS5535
MSR Addressing" on page 53 for more details on MSR
addressing.
All MSRs are 64 bits, however, the UART/IR Controller
Specific MSRs (summarized in Table 5-28) are called out
Bank 0
MSR Address
see Section 5.6.1 on page 299.)
5140003Ah
5140003Bh
5140003Ch
5140003Dh
5140003Eh
5140003Fh
51400038h
51400039h
I/O Offset
00h
01h
02h
03h
04h
05h
06h
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
WO
RO
RO
RO
RO
Table 5-29. UART/IR Controller Native Registers Summary
Table 5-28. UART/IR Controller Specific MSRs Summary
Register Name
UART1 Primary Dongle and Modem Interface
(UART[1]_MOD)
(UART[1]_DONG)
UART1 Interface Configuration (UART[1]_CONF)
UART1 Reserved MSR (UART[1]_RSVD_MSR) -
Reads return 0; writes have no effect.
UART2 Primary Dongle and Modem Interface
(UART[2]_MOD)
(UART[2]_DONG)
UART2 Interface Configuration (UART[2]_CONF)
Reads return 0; writes have no effect.
UART1 Secondary Dongle and Status
UART2 Secondary Dongle and Status
UART2 Reserved MSR (UART[2]_RSVD_MSR) -
Register Name
Receive Data Port (RXD)
Transmit Data Port (TXD)
Interrupt Enable Register (IER)
Event Identification Register (EIR)
FIFO Control Register (FCR)
Link Control Register (LCR)
Bank Select Register (BSR)
Modem/Mode Control Register (MCR)
Link Status Register (LSR)
Modem Status Register (MSR)
360
as 8 bits. The UART/IR Controller treats writes to the upper
56 bits (i.e., bits [63:8]) of the 64-bit MSRs as don’t cares
and always returns 0 on these bits.
The UART/IR Controller Native register set consists of
eight register banks, each containing eight registers, to
control UART operation. All registers use the same 8-byte
address space to indicate I/O Offsets 00h-07h. The Native
registers are accessed via Banks 0 through 7 as I/O Off-
sets. See MSR_LEG_IO (MSR 51400014h) bits [22:20]
and bits [18:16] for setting base address. Each bank and its
offsets are summarized in Table 5-29.
The register summary tables include reset values and page
references where the bit descriptions are provided.
Non-Extended Mode:
Extended Mode: 22h
Reset Value
Reset Value
42h
00h
42h
00h
01h
00h
00h
00h
00h
60h
0xh
xxh
0xh
xxh
xxh
xxh
00h
x0h
Reference
Reference
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