cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 518

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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GLCP Register Descriptions
5.20.2 GLCP Specific MSRs
These registers are used for power management, and facilitate some clock and reset functions. The “CLK” associated reg-
isters (i.e., CLKACTIVE, CLKOFF, CLKDISABLE, CLK4ACK and PMCLKDISABLE) have the same layout where each bit is
associated with a clock domain. The layout and recommended operating values for the “CLK” associated registers is shown
in Table 5-73. For additional discussion on clock management considerations, see Section 3.5 "Clock Considerations" on
page 57.
CLK[63:34] RSVD. Reserved for future use by National.
MSR Bit
CLK33
CLK32
CLK31
CLK30
CLK29
CLK28
CLK26
CLK25
CLK24
CLK23
CLK22
CLK21
CLK20
CLK19
CLK18
CLK17
CLK16
CLK15
CLK14
CLK13
CLK12
CLK11
CLK10
CLk27
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
CLK0
Name/Description
GLCP_PCI. GLCP PCI Clock.
GLCP_DBG. GLCP DBG Logic Clock.
GLCP_GLIU. GLCP GeodeLink Clock.
DIVIL_MFGPT_32K_STD. MFGPT 32 kHz Standby Clock entering
DIVIL.
DIVIL_MFGPT_14M. MFGPT 14 MHz Clock entering DIVIL.
DIVIL_MFGPT_32K. MFGPT 32 kHz Clock entering DIVIL.
DIVIL_GPIO_STD. GPIO Standby Clock entering DIVIL.
DIVIL_GPIO. GPIO Clock entering DIVIL.
DIVIL_PMC_STD. PMC Standby Clock.
DIVIL_PMC. PMC Working Logic Clock.
DIVIL_UART2. UART2 Clock entering DIVIL.
DIVIL_UART1. UART1 Clock entering DIVIL.
DIVIL_PIT. PIT Clock entering DIVIL.
DIVIL_SMB. SMB Clock entering DIVIL.
DIVIL_DMA. DMA Clock entering DIVIL.
DIVIL_LPC. LPC Clock entering DIVIL.
DIVIL_LB. LBus Clock entering DIVIL.
DIVIL_GLIU. GeodeLink (GLIU) Clock entering DIVIL.
ACC_BIT. AC97 Clock entering ACC.
ACC_LB. 33 MHz Clock entering ACC.
ACC_GLIU. GeodeLink (GLIU) Clock entering ACC.
ATAC_LB. 66 MHz Clock entering ATAC.
ATAC_GLIU. GeodeLink (GLIU) Clock entering ATAC.
USB2_48M. 48 MHz Clock entering USB (ports 3 & 4).
USB1_48M. 48 MHz Clock entering USB (ports 1 & 2).
USB2_LB. 33 MHz Clock entering USB (ports 3 & 4).
USB1_LB. 33 MHz Clock entering USB (ports 1 & 2).
USB2_GLIU. GeodeLink (GLIU) Clock entering USB (ports 3 & 4).
USB1_GLIU. GeodeLink (GLIU) Clock entering USB (ports 1 & 2).
GLPCI_PCIF. Fast PCI Clock for chip I/O interface.
GLPCI_PCI. Normal PCI Clock for GLPCI_SB logic.
GLPCI_GLIU. GeodeLink (GLIU) Clock entering GLPCI_SB.
GL0_1. GeodeLink (GLIU) operational logic clock.
GL0_0. GeodeLink (GLIU) clock to timer logic.
Table 5-73. Clock Mapping / Operational Settings
(Continued)
518
ACTIVE
CLK
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
CLK
OFF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GLCP Register
DISABLE
CLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4ACK
CLK
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
DISABLE
Revision 0.8
CLK
PM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0