adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 34

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

www.national.com
16.0 Functional Description
The ADC12D800/500RF is a versatile A/D converter with an
innovative architecture which permits very high speed oper-
ation. The controls available ease the application of the de-
vice to circuit solutions. Optimum performance requires
adherence to the provisions discussed here and in the Appli-
cations Information Section. This section covers an overview,
a description of control modes (Extended Control Mode and
Non-Extended Control Mode), and features.
16.1 OVERVIEW
The ADC12D800/500RF uses a calibrated folding and inter-
polating architecture that achieves a high Effective Number
of Bits (ENOB). The use of folding amplifiers greatly reduces
the number of comparators and power consumption. Interpo-
lation reduces the number of front-end amplifiers required,
minimizing the load on the input signal and further reducing
power requirements. In addition to correcting other non-ide-
alities, on-chip calibration reduces the INL bow often seen
with folding architectures. The result is an extremely fast, high
performance, low power converter.
The analog input signal (which is within the converter's input
voltage range) is digitized to twelve bits at speeds of 200/200
MSPS to 1.6/1.0 GSPS, typical. Differential input voltages
below negative full-scale will cause the output word to consist
of all zeroes. Differential input voltages above positive full-
scale will cause the output word to consist of all ones. Either
of these conditions at the I- or Q-input will cause the Out-of-
Range I-channel or Q-channel output (ORI or ORQ), respec-
tively, to output a logic-high signal.
In ECM, an expanded feature set is available via the Serial
Interface. The ADC12D800/500RF builds upon previous ar-
chitectures, introducing a new DES Mode timing adjust fea-
ture, AutoSync feature for multi-chip synchronization and
increasing to 15-bit for gain and 12-bit plus sign for offset the
independent programmable adjustment for each channel.
Each channel has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 Demux Mode is selected,
the output data rate is reduced to half the input sample rate
on each bus. When Non-Demux Mode is selected, the output
data rate on each channel is at the same rate as the input
sample clock and only one 12-bit bus per channel is active.
16.2 CONTROL MODES
The ADC12D800/500RF may be operated in one of two con-
trol modes: Non-extended Control Mode (Non-ECM) or Ex-
tended Control Mode (ECM). In the simpler Non-ECM (also
sometimes referred to as Pin Control Mode), the user affects
available configuration and control of the device through the
control pins. The ECM provides additional configuration and
control options through a serial interface and a set of 16 reg-
isters, most of which are available to the customer.
16.2.1 Non-Extended Control Mode
In Non-extended Control Mode (Non-ECM), the Serial Inter-
face is not active and all available functions are controlled via
various pin settings. Non-ECM is selected by setting the
ECE Pin to logic-high. Note that, for the control pins, "logic-
high" and "logic-low" refer to V
dedicated control pins provide a wide range of control for the
ADC12D800/500RF and facilitate its operation. These control
pins provide DES Mode selection, Demux Mode selection,
DDR Phase selection, execute Calibration, Calibration Delay
setting, Power Down I-channel, Power Down Q-channel, Test
Pattern Mode selection, and Full-Scale Input Range selec-
tion. In addition to this, two dual-purpose control pins provide
A
and GND, respectively. Nine
34
for AC/DC-coupled Mode selection and LVDS output com-
mon-mode voltage selection. See
16.2.1.1 Dual Edge Sampling Pin (DES)
The Dual Edge Sampling (DES) Pin selects whether the
ADC12D800/500RF is in DES Mode (logic-high) or Non-DES
Mode (logic-low). DES Mode means that a single analog input
is sampled by both I- and Q-channels in a time-interleaved
manner. One of the ADCs samples the input signal on the
rising sampling clock edge (duty cycle corrected); the other
ADC samples the input signal on the falling sampling clock
edge (duty cycle corrected). In Non-ECM, only the I-input may
be used for DES Mode, a.k.a. DESI Mode. In ECM, the Q-
input may be selected via the DEQ Bit (Addr: 0h, Bit: 6), a.k.a.
DESQ Mode. In ECM, both the I- and Q-inputs may be se-
lected, a.k.a. DESIQ Mode.
To use this feature in ECM, use the DES bit in the Configu-
ration Register (Addr: 0h; Bit: 7). See
Non-DES Mode
16.2.1.2 Non-Demultiplexed Mode Pin (NDM)
The Non-Demultiplexed Mode (NDM) Pin selects whether the
ADC12D800/500RF is in Demux Mode (logic-low) or Non-
Demux Mode (logic-high). In Non-Demux Mode, the data from
the input is produced at the sampled rate at a single 12-bit
output bus. In Demux Mode, the data from the input is pro-
duced at half the sampled rate at twice the number of output
buses. For Non-DES Mode, each I- or Q-channel will produce
its data on one or two buses for Non-Demux or Demux Mode,
respectively. For DES Mode, the selected channel will pro-
duce its data on two or four buses for Non-Demux or Demux
Mode, respectively. If Non-Demux Mode is selected, the de-
Dedicated Control Pins
Dual-purpose Control Pins
DDRPh
CalDly
Name
NDM
V
PDQ
TPM
DES
FSR
CAL
V
Pin
PDI
CMO
BG
Lower FS input
TABLE 17. Non-ECM Pin Summary
Shorter delay
Pattern Mode
Falling Mode
AC-coupled
Not allowed
Logic-Low
Q-channel
0° Mode /
Non-DES
operation
I-channel
Non-Test
Demux
Range
Mode
Mode
active
active
Calibration Pin (CAL)
See
for more information.
Section 16.2.1.4
mode voltage
Longer delay
Higher LVDS
Power Down
Power Down
Rising Mode
Non-Demux
Test Pattern
input Range
Logic-High
Not allowed
90° Mode /
Q-channel
Higher FS
I-channel
common-
Mode
Mode
Mode
DES
Table 17
Section 16.3.1.4 DES/
for a summary.
mode voltage
Power Down
Power Down
Lower LVDS
DC-coupled
Q-channel
operation
common-
I-channel
Floating
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid