adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 44

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

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FSR will result in all 1's at the output and an input signal which
is below the FSR will result in all 0's at the output. When the
conversion result is clipped for the I-channel input, the Out-
of-Range I-channel (ORI) output is activated such that ORI+
goes high and ORI- goes low while the signal is out of range.
This output is active as long as accurate data on either or both
of the buses would be outside the range of 000h to FFFh. The
Q-channel has a separate ORQ which functions similarly.
17.1.5 Maximum Input Range
The recommended operating and absolute maximum input
range may be found in
Section 10.0 Absolute Maximum
the stated allowed operating conditions, each Vin+ and Vin-
input pin may be operated in the range from 0V to 2.15V if the
input is a continuous 100% duty cycle signal and from 0V to
2.5V if the input is a 10% duty cycle signal. The absolute
maximum input range for Vin+ and Vin- is from -0.15V to 2.5V.
These limits apply only for input signals for which the input
common mode voltage is properly maintained.
17.1.6 AC-coupled Input Signals
The ADC12D800/500RF analog inputs require a precise
common-mode voltage. This voltage is generated on-chip
when AC-coupling Mode is selected. See
AC/DC-Coupled Mode Pin (V
how to select AC-coupled Mode.
In AC-coupled Mode, the analog inputs must of course be AC-
coupled. For an ADC12D800/500RF used in a typical appli-
cation, this may be accomplished by on-board capacitors, as
shown in
puts on the Reference Board are directly connected to the
analog inputs on the ADC12D800RF, so this may be accom-
plished by DC blocks (included with the hardware kit).
When the AC-coupled Mode is selected, an analog input
channel that is not used (e.g. in DES Mode) should be con-
nected to AC ground, e.g. through capacitors to ground . Do
not connect an unused analog input directly to ground.
The analog inputs for the ADC12D800/500RF are internally
buffered, which simplifies the task of driving these inputs and
the RC pole which is generally used at sampling ADC inputs
is not required. If the user desires to place an amplifier circuit
before the ADC, care should be taken to choose an amplifier
with adequate noise and distortion performance, and ade-
quate gain at the frequencies used for the application.
17.1.7 DC-coupled Input Signals
In DC-coupled Mode, the ADC12D800/500RF differential in-
puts must have the correct common-mode voltage. This volt-
age is provided by the device itself at the V
is recommended to use this voltage because the V
potential will change with temperature and the common-mode
FIGURE 16. AC-coupled Differential Input
Figure
16. For the ADC12D800RFRB, the SMA in-
Section 11.0 Operating Ratings
CMO
Ratings, respectively. Under
)
for more information about
30128644
Section 16.2.1.10
CMO
output pin. It
CMO
output
and
44
voltage of the driving device should track this change. Full-
scale distortion performance falls off as the input common
mode voltage deviates from V
mended to keep the input common-mode voltage within 100
mV of V
±150 mV (maximum). See V
AC- and DC-coupled Mode are similar, provided that the input
common mode voltage at both analog inputs remains within
100 mV of V
17.1.8 Single-Ended Input Signals
The analog inputs of the ADC12D800/500RF are not de-
signed to accept single-ended signals. The best way to han-
dle single-ended signals is to first convert them to differential
signals before presenting them to the ADC. The easiest way
to accomplish single-ended to differential signal conversion is
with an appropriate balun-transformer, as shown in
17.
When selecting a balun, it is important to understand the input
architecture of the ADC. The impedance of the analog source
should be matched to the ADC12D800/500RF's on-chip
100Ω differential input termination resistor. The range of this
termination resistor is specified as R
17.2 THE CLOCK INPUTS
The ADC12D800/500RF has a differential clock input, CLK+
and CLK-, which must be driven with an AC-coupled, differ-
ential clock signal. This provides the level shifting necessary
to allow for the clock to be driven with LVDS, PECL, LVPECL,
or CML levels. The clock inputs are internally terminated to
100Ω differential and self-biased. This section covers cou-
pling, frequency range, level, duty-cycle, jitter, and layout
considerations.
17.2.1 CLK Coupling
The clock inputs of the ADC12D800/500RF must be capaci-
tively coupled to the clock pins as indicated in
FIGURE 17. Single-Ended to Differential Conversion
FIGURE 18. Differential Input Clock Connection
CMO
(typical), although this range may be extended to
CMO
.
Using a Balun
CMI
CMO
in
. Therefore, it is recom-
Table
IN
in
30128647
Table
8. Performance in
Figure
8.
30128643
18.
Figure