adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 43

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

17.0 Applications Information
17.1 THE ANALOG INPUTS
The ADC12D800/500RF will continuously convert any signal
which is present at the analog inputs, as long as a CLK signal
is also provided to the device. This section covers important
aspects related to the analog inputs including: acquiring the
input, driving the ADC in DES Mode, the reference voltage
and FSR, out-of-range indication, AC/DC-coupled signals,
and single-ended input signals.
17.1.1 Acquiring the Input
The Aperture Delay, t
from the sampling edge of the clock input, after which signal
present at the input pin is sampled inside the device. Data is
acquired at the rising edge of CLK+ in Non-DES Mode and
both the falling and rising edges of CLK+ in DES Mode. In
Non-DES Mode, the I- and Q-channels always sample data
on the rising edge of CLK+. In DES Mode, i.e. DESI, DESQ,
DESIQ, and DESCLKIQ, the I-channel samples data on the
rising edge of CLK+ and the Q-channel samples data on the
falling edge of CLK+. The digital equivalent of that data is
available at the digital outputs a constant number of sampling
clock cycles later for the DI, DQ, DId and DQd output buses,
a.k.a. Latency, depending on the demultiplex mode which is
selected. In addition to the Latency, there is a constant output
delay, t
t
14.
17.1.2 Driving the ADC in DES Mode
The ADC12D800/500RF can be configured as either a 2-
channel, 800/500 GSPS device (Non-DES Mode) or a 1-
channel 1.6/1.0 GSPS device (DES Mode). When the device
is configured in DES Mode, there is a choice for with which
input to drive the single-channel ADC. These are the 3 op-
tions:
DES – externally driving the I-channel input only. This is the
default selection when the ADC is configured in DES Mode.
It may also be referred to as “DESI” for added clarity.
DESQ – externally driving the Q-channel input only.
DESIQ, DESCLKIQ – externally driving both the I- and Q-
channel inputs. VinI+ and VinQ+ should be driven with the
exact same signal. VinI- and VinQ- should be driven with the
exact same signal, which is the differential compliment to the
one driving VinI+ and VinQ+.
The input impedance for each I- and Q-input is 100Ω differ-
ential (or 50Ω single-ended), so the trace to each VinI+, VinI-,
VinQ+, and VinQ- should always be 50Ω single-ended. If a
single I- or Q-input is being driven, then that input will present
a 100Ω differential load. For example, if a 50Ω single-ended
source is driving the ADC, then a 1:2 balun will transform the
impedance to 100Ω differential. However, if the ADC is being
driven in DESIQ Mode, then the 100Ω differential impedance
from the I-input will appear in parallel with the Q-input for a
composite load of 50Ω differential and a 1:1 balun would be
appropriate. See
ADC in DESIQ Mode. A recommended part selection is using
the Mini-Circuits TC1-1-13MA+ balun with Ccouple = 0.22µF.
OD
in the Timing Diagrams. See t
OD
, before the data is available at the outputs. See
Figure 15
AD
, is the amount of delay, measured
for an example circuit driving the
LAT
, t
AD
, and t
OD
in
Table
43
In the case that only one channel is used in Non-DES Mode
or that the ADC is driven in DESI or DESQ Mode, the unused
analog input should be terminated to reduce any noise cou-
pling into the ADC. See
17.1.3 FSR and the Reference Voltage
The full-scale analog differential input range (V
ADC12D800/500RF is derived from an internal bandgap ref-
erence. In Non-ECM, this full-scale range has two settings
controlled by the FSR Pin; see
Input Range Pin
Q-channels. In ECM, the full-scale range may be indepen-
dently set for each channel via Addr:3h and Bh with 15 bits
of precision; see
SNR is obtained with a higher full-scale input range, but better
distortion and SFDR are obtained with a lower full-scale input
range. It is not possible to use an external analog reference
voltage to modify the full-scale range, and this adjustment
should only be done digitally, as described.
A buffered version of the internal bandgap reference voltage
is made available at the V
drive a load of up to 80 pF and source or sink up to 100 μA.
It should be buffered if more current than this is required. This
pin remains as a constant reference voltage regardless of
what full-scale range is selected and may be used for a sys-
tem reference. V
used to select a higher LVDS output common-mode voltage;
see
(V
17.1.4 Out-Of-Range Indication
Differential input signals are digitized to 12 bits, based on the
full-scale range. Signal excursions beyond the full-scale
range, i.e. greater than +V
be clipped at the output. An input signal which is above the
Non-DES
Non-DES
Non-DES
BG
Mode
DES/
DES/
TABLE 25. Unused Analog Input Recommended
).
Section 16.2.1.11 LVDS Output Common-mode Pin
FIGURE 15. Driving DESIQ Mode
Power
Down
Yes
No
No
(FSR). The FSR Pin operates on both I- and
BG
Section 18.0 Register
is a dual-purpose pin and it may also be
Coupling
Termination
Table 25
AC/DC
BG
IN_FSR
DC
AC
Pin for the user. The V
/2 or less than -V
Section 16.2.1.9 Full-Scale
for details.
Tie Unused+ to Unused-
Tie Unused+ and
Tie Unused+ and
Recommended
Unused- to Vbg
Unused- to Vbg
Definitions. The best
Termination
IN_FSR
IN_FSR
www.national.com
BG
30128613
) of the
pin can
/2, will