adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 59

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

AutoSync
(Note
Reserved
Addr: Eh (1110b)
Bits 15:7
Bit 6
Bit 5
Bits 4:3
Bit 2
Bit 1
Bit 0
Addr: Fh (1111b)
Bits 15:0
Name
Name
POR
POR
Bit
Bit
17)
15
15
0
0
DRC(8:0): Delay Reference Clock (8:0). These bits may be used to increase the delay on the input reference
clock when synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of
1200 ps (319d). The delay remains the maximum of 1200 ps for any codes above or equal to 319d. See
Section 17.4 SYNCHRONIZING MULTIPLE ADC12D800/500RFS IN A SYSTEM
DCK: DESCLKIQ Mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples
the I- and Q-channels 180º out of phase with respect to one another, i.e. the DESCLKIQ Mode. To select the
DESCLKIQ Mode, Addr: 0h, Bits <7:5> must also be set to 000b. See
for more information.
Reserved. Must be set as shown.
SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond
to the following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided
clocks are synchronized with the reference clock coming from the master ADC. The master clock is applied on
the input pins RCLK. If this bit is set to 0b, then the device is in Master Mode.
DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The
default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the
device is operating in Master or Slave Mode, as determined by ES (Bit 2).
DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to
enable DCLK_RST functionality.
Reserved. This address is read only.
14
14
0
0
13
13
0
0
12
12
0
0
(Note
DRC(8:0)
11
11
0
17)
0
10
10
0
0
9
0
9
0
59
8
0
8
0
Res
7
0
7
0
DCK
6
0
6
0
Res
Section 16.3.1 Input Control and Adjust
5
0
5
0
4
0
4
1
SP(1:0)
for more information.
3
0
3
1
ES
POR state: 001Dh
POR state: 0003h
2
0
2
1
DOC
1
1
1
0
www.national.com
DR
0
1
0
1