adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 35

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

fault is DDR Mode. If Demux Mode is selected, the default is
SDR Mode.
This feature is pin-controlled only and remains active during
both Non-ECM and ECM. See
demux Mode
16.2.1.3 Dual Data Rate Phase Pin (DDRPh)
The Dual Data Rate Phase (DDRPh) Pin selects whether the
ADC12D800/500RF is in 0° Mode (logic-low) or 90° Mode
(logic-high) for DDR Mode. If the device is in SDR Mode, then
the DDRPh Pin selects whether the ADC12D800/500RF is in
Falling Mode (logic-low) or Rising Mode (logic-high). For DDR
Mode, the Data may transition either with the DCLK transition
(0° Mode) or halfway between DCLK transitions (90° Mode).
The DDRPh Pin selects the mode for both the I-channel: DI-
and DId-to-DCLKI phase relationship and for the Q-channel:
DQ- and DQd-to-DCLKQ phase relationship.
To use this feature in ECM, use the DPS bit in the Configu-
ration Register (Addr: 0h; Bit: 14). See
DDR Clock
16.2.1.4 Calibration Pin (CAL)
The Calibration (CAL) Pin may be used to execute an on-
command calibration or to disable the power-on calibration.
The effect of calibration is to maximize the dynamic perfor-
mance. To initiate an on-command calibration via the CAL
pin, bring the CAL pin high for a minimum of t
cycles after it has been low for a minimum of t
cycles. Holding the CAL pin high upon power-on will prevent
execution of the power-on calibration. In ECM, this pin re-
mains active and is logically OR'd with the CAL bit.
To use this feature in ECM, use the CAL bit in the Configu-
ration Register (Addr: 0h; Bit: 15). See
bration Feature
16.2.1.5 Calibration Delay Pin (CalDly)
The Calibration Delay (CalDly) Pin selects whether a shorter
or longer delay time is present, after the application of power,
until the start of the power-on calibration. The actual delay
time is specified as t
feature is pin-controlled only and remains active in ECM. It is
recommended to select the desired delay time prior to power-
on and not dynamically alter this selection.
See
16.2.1.6 Power Down I-channel Pin (PDI)
The Power Down I-channel (PDI) Pin selects whether the I-
channel is powered down (logic-high) or active (logic-low).
The digital data output pins, DI and DId, (both positive and
negative) are put into a high impedance state when the I-
channel is powered down. Upon return to the active state, the
pipeline will contain meaningless information and must be
flushed. The supply currents (typicals and limits) are available
for the I-channel powered down or active and may be found
in
power-cycle of PDI (or PDQ).
This pin remains active in ECM. In ECM, either this pin or the
PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used
Table
Section 16.3.3 Calibration Feature
13. The device should be recalibrated following a
for more information.
for more information.
for more information.
CalDly
and may be found in
Section 16.3.2.5 Demux/Non-
Section 16.3.2.1 SDR /
for more information.
Section 16.3.3 Cali-
CAL_H
CAL_L
Table
input clock
input clock
16. This
35
to power-down the I-channel. See
Down
16.2.1.7 Power Down Q-channel Pin (PDQ)
The Power Down Q-channel (PDQ) Pin selects whether the
Q-channel is powered down (logic-high) or active (logic-low).
This pin functions similarly to the PDI pin, except that it applies
to the Q-channel. The PDI and PDQ pins function indepen-
dently of each other to control whether each I- or Q-channel
is powered down or active.
This pin remains active in ECM. In ECM, either this pin or the
PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be
used to power-down the Q-channel. See
er Down
16.2.1.8 Test Pattern Mode Pin (TPM)
The Test Pattern Mode (TPM) Pin selects whether the
output of the ADC12D800/500RF is a test pattern (logic-high)
or
ADC12D800/500RF can provide a test pattern at the four out-
put buses independently of the input signal to aid in system
debug. In TPM, the ADC is disengaged and a test pattern
generator is connected to the outputs, including ORI and
ORQ.
mation.
16.2.1.9 Full-Scale Input Range Pin (FSR)
The Full-Scale Input Range (FSR) Pin selects whether the
full-scale input range for both the I- and Q-channel is higher
(logic-high) or lower (logic-low). The input full-scale range is
specified as V
input range for each I- and Q-channel may not be set inde-
pendently, but it is possible to do so in ECM. The device must
be calibrated following a change in FSR to obtain optimal
performance.
To use this feature in ECM, use the Configuration Registers
(Addr: 3h and Bh). See
just
16.2.1.10 AC/DC-Coupled Mode Pin (V
The V
output, it provides the optimal common-mode voltage for the
DC-coupled analog inputs. When functioning as an input, it
selects whether the device is AC-coupled (logic-low) or DC-
coupled (floating). This pin is always active, in both ECM and
Non-ECM.
16.2.1.11 LVDS Output Common-mode Pin (V
The V
output, it provides the bandgap reference. When functioning
as an input, it selects whether the LVDS output common-
mode voltage is higher (logic-high) or lower (floating). The
LVDS output common-mode voltage is specified as V
may be found in
ECM and Non-ECM.
for more information.
the
CMO
BG
for more information.
SeeSection 16.3.2.6 Test Pattern Mode
for more information.
Pin serves a dual purpose. When functioning as an
Pin serves a dual purpose. When functioning as an
converted
IN_FSR
Table
in
12. This pin is always active, in both
Table
Section 16.3.1 Input Control and Ad-
analog
8. In Non-ECM, the full-scale
input
Section 16.3.4 Power
Section 16.3.4 Pow-
CMO
(logic-low).
)
for more infor-
www.national.com
BG
)
OS
The
and