adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 5

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

18.0 Register Definitions ...................................................................................................................... 53
19.0 Physical Dimensions .................................................................................................................... 60
FIGURE 1. ADC12D800/500RF Connection Diagram ........................................................................................ 3
FIGURE 2. LVDS Output Signal Levels ......................................................................................................... 28
FIGURE 3. Input / Output Transfer Characteristic ............................................................................................ 30
FIGURE 4. Clocking in 1:2 Demux Non-DES Mode* ......................................................................................... 31
FIGURE 5. Clocking in Non-Demux Non-DES Mode* ........................................................................................ 31
FIGURE 6. Clocking in 1:4 Demux DES Mode* ............................................................................................... 32
FIGURE 7. Clocking in Non-Demux Mode DES Mode* ...................................................................................... 32
FIGURE 8. Data Clock Reset Timing (Demux Mode) ........................................................................................ 33
FIGURE 9. Power-on and On-Command Calibration Timing ................................................................................ 33
FIGURE 10. Serial Interface Timing ............................................................................................................. 33
FIGURE 11. Serial Data Protocol - Read Operation .......................................................................................... 36
FIGURE 12. Serial Data Protocol - Write Operation .......................................................................................... 37
FIGURE 13. DDR DCLK-to-Data Phase Relationship ........................................................................................ 40
FIGURE 14. SDR DCLK-to-Data Phase Relationship ........................................................................................ 40
FIGURE 15. Driving DESIQ Mode ............................................................................................................... 43
FIGURE 16. AC-coupled Differential Input ..................................................................................................... 44
FIGURE 17. Single-Ended to Differential Conversion Using a Balun ...................................................................... 44
FIGURE 18. Differential Input Clock Connection .............................................................................................. 44
FIGURE 19. AutoSync Example ................................................................................................................. 46
FIGURE 20. Power and Grounding Example .................................................................................................. 48
FIGURE 21. HSBGA Conceptual Drawing ..................................................................................................... 48
FIGURE 22. Power-on with Control Pins set by Pull-up/down Resistors .................................................................. 50
FIGURE 23. Power-on with Control Pins set by FPGA pre Power-on Cal ................................................................ 50
FIGURE 24. Power-on with Control Pins set by FPGA post Power-on Cal ............................................................... 50
FIGURE 25. Supply and DCLK Ramping ....................................................................................................... 51
FIGURE 26. Typical Temperature Sensor Application ....................................................................................... 51
TABLE 1. Analog Front-End and Clock Balls ................................................................................................... 7
TABLE 2. Control and Status Balls .............................................................................................................. 10
17.2 THE CLOCK INPUTS ........................................................................................................... 44
17.3 THE LVDS OUTPUTS ........................................................................................................... 45
17.4 SYNCHRONIZING MULTIPLE ADC12D800/500RFS IN A SYSTEM ........................................... 45
17.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS ................................. 47
17.6 SYSTEM POWER-ON CONSIDERATIONS ............................................................................. 49
17.7 RECOMMENDED SYSTEM CHIPS ........................................................................................ 51
17.1.5 Maximum Input Range ................................................................................................ 44
17.1.6 AC-coupled Input Signals ............................................................................................ 44
17.1.7 DC-coupled Input Signals ............................................................................................ 44
17.1.8 Single-Ended Input Signals .......................................................................................... 44
17.2.1 CLK Coupling ............................................................................................................. 44
17.2.2 CLK Frequency .......................................................................................................... 45
17.2.3 CLK Level .................................................................................................................. 45
17.2.4 CLK Duty Cycle .......................................................................................................... 45
17.2.5 CLK Jitter .................................................................................................................. 45
17.2.6 CLK Layout ................................................................................................................ 45
17.3.1 Common-mode and Differential Voltage ......................................................................... 45
17.3.2 Output Data Rate ........................................................................................................ 45
17.3.3 Terminating Unused LVDS Output Pins ......................................................................... 45
17.4.1 AutoSync Feature ....................................................................................................... 46
17.4.2 DCLK Reset Feature ................................................................................................... 46
17.5.1 Power Planes ............................................................................................................. 47
17.5.2 Bypass Capacitors ...................................................................................................... 47
17.5.3 Ground Planes ........................................................................................................... 47
17.5.4 Power System Example ............................................................................................... 47
17.5.5 Thermal Management ................................................................................................. 48
17.6.1 Power-on, Configuration, and Calibration ....................................................................... 49
17.6.2 Power-on and Data Clock (DCLK) ................................................................................. 50
17.7.1 Temperature Sensor ................................................................................................... 51
17.7.2 Clocking Device ......................................................................................................... 51
17.7.3 Amplifiers for the Analog Input ...................................................................................... 52
17.7.4 Balun Recommendations for Analog Input ...................................................................... 52
List of Figures
List of Tables
5
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