adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 58

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

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Q-channel Full-Scale Range Adjust
Aperture Delay Coarse Adjust
Aperture Delay Fine Adjust
Bits 15:4
Bit 3
Bit 2
Bits 1:0
Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will
Bit 9
Bit 8
Bits 7:0
Addr: Bh (1011b)
Bit 15
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The
Addr: Ch (1100b)
Addr: Dh (1101b)
Name
Name
Name
POR
POR
POR
Bit
Bit
Bit
Res
15
15
15
0
0
0
Reserved. Must be set to 0b.
range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is
guaranteed by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low)
setting in Non-ECM. A greater range of FSR values is available in ECM, i.e. FSR values above 800 mV. See
V
Code
000 0000 0000 0000
100 0000 0000 0000 (default)
111 1111 1111 1111
CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to
the input CLK signal. The range is 0 ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for
CAM(11:0) = 2431d (±95 ps due to PVT variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above,
the delay saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh.
Either STA (Bit 3) or SA (Addr: Dh, Bit 8) must be selected to enable this function.
STA: Select t
adjustment settings, i.e. CAM(11:0) and FAM(5:0), available.
DCC: Duty Cycle Correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the
chip. This feature is enabled by default.
Reserved. Must be set to 0b.
be applied to the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3) or SA
(Addr: Dh, Bit 8). The range is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for
FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of ~36 fs.
Reserved. Must be set to 0b.
SA: Select t
Bit 3), except that if SA is enabled, then the value of the STA bit is ignored.
Reserved. Must be set as shown.
IN_FSR
14
14
14
1
0
0
in
Table 8
AD
13
13
13
FAM(5:0)
0
0
AD
0
Adjust. Set this bit to 1b to enable the t
Adjust. Set this bit to 1b to enable the t
for characterization details.
12
12
12
0
0
0
11
11
11
0
0
0
CAM(11:0)
10
10
10
0
0
0
Res
9
0
9
0
9
0
FSR [mV]
600
800
1000
SA
58
8
0
8
0
8
0
FM(14:0)
AD
AD
adjust feature. This bit is the same as STA (Addr: Ch,
7
0
7
0
7
0
adjust feature, which will make both coarse and fine
6
0
6
0
6
0
5
0
5
0
5
0
4
0
4
0
4
0
Res
STA
3
0
3
0
3
0
DCC
POR state: 4000h
POR state: 0004h
POR state: 0000h
2
0
2
1
2
0
1
0
1
0
1
0
Res
0
0
0
0
0
0