adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 55

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

Reserved
I-channel Offset Adjust
I-channel Full Scale Range Adjust
Addr: 1h (0001b)
Addr: 2h (0010b)
Addr: 3h (0011b)
Name
Bits 15:0 Reserved. Must be set as shown.
Name
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight
Name
Bit 15
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The
POR
POR
POR
Bit
Bit
Bit
Res
15
15
15
0
0
0
OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC
output. Setting this bet to 1b incurs a negative offset of the set magnitude.
binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV.
Monotonicity is guaranteed by design only for the 9 MSBs.
Code
0000 0000 0000 (default)
1000 0000 0000
1111 1111 1111
Reserved. Must be set to 0b.
range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is
guaranteed by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low)
setting in Non-ECM. A greater range of FSR values is available in ECM, i.e. FSR values above 800 mV. See
V
Code
000 0000 0000 0000
100 0000 0000 0000 (default)
111 1111 1111 1111
IN_FSR
Res
14
14
14
0
0
1
in
Table 8
13
13
13
1
0
0
for characterization details.
OS
12
12
12
0
0
0
11
11
11
1
0
0
10
10
10
0
0
0
9
0
9
0
9
0
Offset [mV]
0
22.5
45
FSR [mV]
600
800
1000
55
8
1
8
0
8
0
Res
FM(14:0)
7
0
7
0
7
0
OM(11:0)
6
0
6
0
6
0
5
0
5
0
5
0
4
0
4
0
4
0
3
0
3
0
3
0
POR state: 2907h
POR state: 0000h
POR state: 4000h
2
1
2
0
2
0
1
1
1
0
1
0
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0
1
0
0
0
0