adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 54

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

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Configuration Register 1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bits 1:0
Addr: 0h (0000b)
Name CAL
POR
Bit
15
0
CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset
automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to
1b again to execute another calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set
to 0b before either is used to execute a calibration.
DPS: DCLK Phase Select. In DDR, set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship
and to 1b to select the 90° Mode. Note that for 1:2 Demux Mode, the Dual Data Rate (DDR) is not available. In
SDR, set this bit to 0b to transition the data on the Rising edge of DCLK; set this bit to 1b to transition the data
on the Falling edge of DCLK.
OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR,
and DCLK. 0b selects the lower level and 1b selects the higher level. See V
TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the
digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was
present at the analog inputs. See
PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the
I-channel is powered-down. The I-channel may be powered-down via this bit or the PDI Pin, which is active, even
in ECM.
PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to
1b, the Q-channel is powered-down. The Q-channel may be powered-down via this bit or the PDQ Pin, which is
active, even in ECM.
Reserved. Must be set as shown.
Reserved. Must be set as shown.
DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode;
when it is set to 1b, the device will operate in the DES Mode. See
information.
DEQ: DES Q-input select, a.k.a. DESQ Mode. When the device is in DES Mode, this bit selects the input that
the device will operate on. The default setting of 0b selects the I-input and 1b selects the Q-input.
DIQ: DES I- and Q-input, a.k.a. DESIQ Mode. When in DES Mode, setting this bit to 1b shorts the I- and Q-inputs
internally to the device. If the bit is left at its default 0b, the I- and Q-inputs remain electrically separate. In this
mode, both the I- and Q-inputs must be externally driven; see
information.
The allowed DES Modes settings are shown below. For DESCLKIQ Mode, see Addr Eh.
Mode
Non-DES Mode
DESI Mode
DESQ Mode
DESIQ Mode
DESCLKIQ Mode
2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when
set to 1b, the data is output in Two's Complement format.
TSE: Time Stamp Enable. For the default setting of 0b, the Time Stamp feature is not enabled; when set to
1b, the feature is enabled. See
(Note
SDR: Single Data Rate. For the default setting of 0b, the data is clocked in Dual Data Rate; when set to 1b, the
data is clocked in Single Data Rate. See
this feature. Note that for DDR Mode, the 1:2 Demux Mode is not available. See
available modes.
Reserved. Must be set as shown.
DPS
14
0
18)
OVS
(Note
13
1
TPM
18)
12
0
PDI
11
Addr 0h, Bit<7:5>
000b
100b
110b
101b
000b
0
(Note
Section 16.3.2 Output Control and Adjust
PDQ
Section 16.3.2.6 Test Pattern Mode
10
0
18)
Res
Section 16.3.2 Output Control and Adjust
9
0
Res
54
8
0
(Note
DES
Addr Eh, Bit<6>
0b
0b
0b
0b
1b
7
0
18)
(Note
DEQ
Section 16.3.1.4 DES/Non-DES Mode
6
0
Section 16.3.1.4 DES/Non-DES Mode
18)
DIQ
for details about the TPM pattern.
5
0
for more information about this feature.
OD
2SC
4
0
in
Table 21
Table 12
for more information about
TSE
3
0
for a selection of
SDR
for details.
POR state: 2000h
2
0
1
0
for more
Res
for more
0
0