adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 57

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

DES Timing Adjust
(Note
Reserved
Reserved
Q-channel Offset Adjust
Addr: 7h (0111b)
Bits 15:9
Bits 8:0
Addr: 8h (1000b)
Bits 15:0
Addr: 9h (1001b)
Bits 15:0
Addr: Ah (1010b)
Name
Name
Name
Name
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight
POR
POR
POR
POR
Bit
Bit
Bit
Bit
17)
15
15
15
15
1
0
0
0
OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC
output. Setting this bet to 1b incurs a negative offset of the set magnitude.
binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV.
Monotonicity is guaranteed by design only for the 9 MSBs.
Code
0000 0000 0000 (default)
1000 0000 0000
1111 1111 1111
DTA(6:0): DES Mode Timing Adjust. In the DES Mode, the time at which the falling edge sampling clock samples
relative to the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues
to function. See
Reserved. Must be set as shown.
Reserved. Must be set as shown.
Reserved. Must be set as shown.
Res
14
14
14
14
0
0
0
0
13
13
13
13
0
0
0
0
Section 16.3.1 Input Control and Adjust
DTA(6:0)
OS
12
12
12
12
0
0
0
0
11
11
11
11
0
1
0
0
10
10
10
10
0
1
0
0
9
0
9
1
9
0
9
0
Offset [mV]
0
22.5
45
57
8
1
8
1
8
0
8
0
Res
Res
for more information. The nominal step size is 30fs.
7
0
7
0
7
0
7
0
OM(11:0)
6
1
6
0
6
0
6
0
5
0
5
0
5
0
5
0
Res
4
0
4
0
4
0
4
0
3
0
3
1
3
0
3
0
POR state: 0F0Fh
POR state: 8142h
POR state: 0000h
POR state: 0000h
2
0
2
1
2
0
2
0
1
1
1
1
1
0
1
0
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0
0
0
1
0
0
0
0