adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 39

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

16.3.1 Input Control and Adjust
There are several features and configurations for the input of
the ADC12D800/500RF so that it may be used in many dif-
ferent applications. This section covers AC/DC-coupled
Mode, input full-scale range adjust, input offset adjust, DES/
Non-DES Mode, and sampling clock phase adjust.
16.3.1.1 AC/DC-coupled Mode
The analog inputs may be AC or DC-coupled. See
tion 16.2.1.10 AC/DC-Coupled Mode Pin (V
tion on how to select the desired mode and
DC-coupled Input Signals
put Signals
16.3.1.2 Input Full-Scale Range Adjust
The input full-scale range for the ADC12D800/500RF may be
adjusted via Non-ECM or ECM. In Non-ECM, a control pin
selects a higher or lower value; see
Scale Input Range Pin
range may be adjusted with 15-bits of precision. See
V
the higher and lower full-scale input range settings in Non-
ECM correspond to the mid and min full-scale input range
settings in ECM. It is necessary to execute an on-command
calibration following a change of the input full-scale range.
See
the registers.
16.3.1.3 Input Offset Adjust
The input offset adjust for the ADC12D800/500RF may be
adjusted with 12-bits of precision plus sign via ECM. See
Section 18.0 Register Definitions
registers.
16.3.1.4 DES/Non-DES Mode
The ADC12D800/500RF can operate in Dual-Edge Sampling
(DES) or Non-DES Mode. The DES Mode allows for a single
analog input to be sampled by both I- and Q-channels. One
channel samples the input on the rising edge of the sampling
clock and the other samples the same input signal on the
falling edge of the sampling clock. A single input is thus sam-
pled twice per clock cycle, resulting in an overall sample rate
of twice the sampling clock frequency, e.g. 1.6/1.0 GSPS with
a 800/500 MHz sampling clock. Since DES Mode uses both
I- and Q-channels to process the input signal, both channels
must be powered up for the DES Mode to function properly.
In Non-ECM, only the I-input may be used for the DES Mode
input. See
for information on how to select the DES Mode. In ECM, either
the I- or Q-input may be selected by first using the DES bit
(Addr: 0h, Bit 7) to select the DES Mode. The DEQ Bit (Addr:
0h, Bit: 6) is used to select the Q-input, but the I-input is used
by default. Also, both I- and Q-inputs may be driven externally,
IN_FSR
Power down Q-channel
Read/Write Calibration
Power down I-channel
Section 18.0 Register Definitions
Calibration Adjust
Settings
in
Table 8
Section 16.2.1.1 Dual Edge Sampling Pin (DES)
(Note
for applications information.
Feature
(Note
17)
for electrical specification details. Note that
17)
(FSR). In ECM, the input full-scale
and
Section 17.1.6 AC-coupled In-
Selected via PDQ
Selected via PDI
for information about the
Not available
Not available
Non-ECM
Section 16.2.1.9 Full-
(Pin U3)
(Pin V3)
for information about
CMO
Section 17.1.7
)
for informa-
Active in ECM
Sec-
Control Pin
Power-Down
N/A
N/A
Yes
Yes
39
i.e. DESIQ Mode, by using the DIQ bit (Addr: 0h, Bit 5). See
Section 17.1 THE ANALOG INPUTS
about how to drive the ADC in DES Mode.
In DESCLKIQ Mode, the I- and Q-channels sample their in-
puts 180° out-of-phase with respect to one another, similar to
the other DES Modes. DESCLKIQ Mode is similar to the DE-
SIQ Mode, except that the I- and Q-channels remain electri-
cally separate internal to the ADC12D800/500RF. For this
reason, both I- and Q-inputs must be externally driven for the
DESCLKIQ Mode. The DCK Bit (Addr: Eh, Bit: 6) is used to
select the 180° sampling clock mode.
The DESCLKIQ Mode results in the best bandwidth for the
interleaved modes. In general, the bandwidth decreases from
Non-DES Mode to DES Mode (specifically, DESI or DESQ)
because both channels are sampling off the same input signal
and non-ideal effects introduced by interleaving the two chan-
nels lower the bandwidth. Driving both I- and Q-channels
externally (DESIQ Mode and DESCLKIQ Mode) results in
better bandwidth because each channel is being driven,
which reduces routing losses. The DESCLKIQ Mode has bet-
ter bandwidth than the DESIQ Mode because the routing
internal to the ADC12D800/500 is simpler, which results in
less insertion loss.
In the DES Mode, the outputs must be carefully interleaved
in order to reconstruct the sampled signal. If the device is
programmed into the 1:4 Demux DES Mode, the data is ef-
fectively demultiplexed by 1:4. If the sampling clock is
800/500 MHz, the effective sampling rate is doubled to 1.6/1.0
GSPS and each of the 4 output buses has an output rate of
400/250 MSPS. All data is available in parallel. To properly
reconstruct the sampled waveform, the four bytes of parallel
data that are output with each DCLK must be correctly inter-
leaved. The sampling order is as follows, from the earliest to
the latest: DQd, DId, DQ, DI. See
programmed into the Non-Demux DES Mode, two bytes of
parallel data are output with each edge of the DCLK in the
following sampling order, from the earliest to the latest: DQ,
DI. See
16.3.1.5 DES Timing Adjust
The performance of the ADC12D800/500RF in DES Mode
depends on how well the two channels are interleaved, i.e.
that the clock samples either channel with precisely a 50%
duty-cycle, each channel has the same offset (nominally code
2047/2048), and each channel has the same full-scale range.
The ADC12D800/500RF includes an automatic clock phase
background adjustment in DES Mode to automatically and
continuously adjust the clock phase of the I- and Q-channels.
In addition to this, the residual fixed timing skew offset may
be further manually adjusted, and further reduce timing spurs
for specific applications. See the DES Timing Adjust (Addr:
7h). As the DES Timing Adjust is programmed from 0d to
Selected via the Config Reg
Selected via the PDQ Bit
Selected via the SSC Bit
Selected via the PDI Bit
Figure
(Addr: 0h; Bit: 11)
(Addr: 0h; Bit: 10)
(Addr: 4h; Bit: 7)
(Addr: 4h)
7.
ECM
R/W calibration values
Q-channel operational
Figure
I-channel operational
Default ECM State
for more information
disabled
6. If the device is
t
CAL
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