tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 191

• Manufacturer Part Number: tda5235
• Description: Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
• Manufacturer: Infineon Technologies Corporation

Field
WUBCNT
RSSI Wake-Up Threshold for Channel 1 Register
A_WURSSITH1
RSSI Wake-Up Threshold for Channel 1
Register
Field
WURSSITH1
RSSI Wake-Up Blocking Level Low Channel 1 Register
A_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
Data Sheet
Bits
6:0
Bits
7:0
Type
w
Type
w
Description
Wake Up Bit/Chip Count Register (unit is bits; only exception is WU
Pattern Chip Mode, where unit is chips, see A_WUC.WUPMSEL)
Counter Register to define the maximum counts of bits/chips for Wake Up
detection.
Min: 00h = 0 Bits/Chips to count
In Random Bits or Equal Bits Mode this will cause a Wake Up
on Data Criterion immediately after Symbol Synchronization is found.
In Pattern Detection Mode this will cause no Wake Up on Data Criterion.
In this
Mode there is needed minimum 11h = 17 Bits/Chips to shift
one Pattern through the whole Pattern Detector. Because
comparision can only be started when at least the comparision
register is completely filled.
Max: 7Fh: 127 Bits/Chips to count after Symbol Sync found
Reset: 00
Description
Wake Up on RSSI Threshold level for Channel 1
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00
H
H
Offset
Offset
01B
01C
191
H
H
Register Description
V1.0, 2010-02-19
Reset Value
Reset Value
Appendix
TDA5235
FF
00
H
H